Sfoglia per Relatore
Hardware accelerators of convolutional neural networks. Fused-layer approach
2017/2018 BABIC, DANIJELA
A HW/SW co-design framework for TinyML acceleration
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Information-leakage analysis based on hardware performance counters
2016/2017 FUSI, MATTEO MARIA
Machine learning for species diversification dynamics
2023/2024 COLBERTALDO, MATTIA
Mapping and tuning neural networks on hardware accelerators
2025/2026 Indirli, Fabrizio
Mapping GEMMs on spatial architectures through adaptive programming and greedy optimization
2023/2024 Ronzani, Marco
Modeling and exploration of AI accelerators based on digital in-memory-computing
2025/2026 de Gennaro, Valeria
Near-threshold computing with performance guarantees for manycore architecture
STAMELAKOS, IOANNIS
An online teaching approach to computer architecture
2021/2022 Cazzaniga, Simone Shawn
Parallelized convolutions for embedded ultra low-power deep learning architectures
2017/2018 CUNIAL, LORENZO
A performance analysis method for CNN inference on hardware architectures
2021/2022 CECINI, MATTEO
qGamma: an exploration framework for the mapping of mixed-precision quantized DNN models on hardware accelerators
2023/2024 ALTAMURA, LUIGI
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