Sfoglia per Relatore
Code generation for hybrid hardware-software mapping of deep convolutional neural networks on dataflow neural processing units
2018/2019 BUSCHINI, ALESSANDRO
Compiler autotuning using machine learning techniques
ASHOURI, AMIR HOSSEIN
Design space exploration methodology for compiler parameters in VLIW processors
2012/2013 ASHOURI, AMIR HOSSEIN
Design space exploration of openCL applications on heterogeneous parallel platforms
PAONE, EDOARDO
Efficient OpenCL application autotuning for heterogeneous platforms
2015/2016 ERDEM, AHMET
Exploration and mapping of deep neural networks to low-power hardware accelerators and FPGAs
2020/2021 Erdem, Ahmet
Hardware accelerators of convolutional neural networks. Fused-layer approach
2017/2018 BABIC, DANIJELA
A HW/SW co-design framework for TinyML acceleration
2021/2022 BRUNO, NUNZIO MARIA ALBERTO
Information-leakage analysis based on hardware performance counters
2016/2017 FUSI, MATTEO MARIA
Near-threshold computing with performance guarantees for manycore architecture
STAMELAKOS, IOANNIS
An online teaching approach to computer architecture
2021/2022 Cazzaniga, Simone Shawn
Parallelized convolutions for embedded ultra low-power deep learning architectures
2017/2018 CUNIAL, LORENZO
A performance analysis method for CNN inference on hardware architectures
2021/2022 CECINI, MATTEO
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