Sfoglia per Relatore
C-based high level synthesis of parallel applications targeting adaptive hardware components
CASTELLANA, VITO GIOVANNI
Code transformation in high level synthesis for iterative stencils
2014/2015 VITALI, EMANUELE
Complex FPGA memory controller for irregular memory applications
2016/2017 DEVECCHI, STEFANO
Context switch in hardware accelerator
2016/2017 SAPORETTI, NICOLA
A design flow based on halide and Bambu-HLS to deploy deep learning models on FPGA
2019/2020 GHITTI, MARCO
Discrepancy analysis: a methodology for automated bug detection in hardware designs generated with high-Level synthesis
FEZZARDI, PIETRO
Empowering high-level synthesis methodologies with an OpenMP runtime
2021/2022 GOZZI, GIOVANNI
Flexible experimental embedde satellite : onboard satellite software development
2020/2021 Ampolo, Stefano
An FPGA toolchain for Graph Neural Network acceleration using high-level synthesis
2022/2023 Demasi, Giovanni
Harnessing adaptivity analysis for the automatic design of efficient embedded and HPC systems
LOVERGINE, SILVIA
Integrating components generated with high-level synthesis on a cloud computing platform
2018/2019 SPINA, MASSIMO
Una metodologia per l'identificazione dei punti critici in applicazioni hard real time
2009/2010 GUFFANTI, FRANCESCO MARIA FELICE GASTONE
Una metodologia per la stima di prestazioni di sistemi embedded basata su distribuzioni di probabilità
2009/2010 DE MARCO, LUCA
Modern high-level synthesis : improving productivity with a multi-level approach
2022/2023 Curzel, Serena
Pipelined architectures for HLS generated designs
2018/2019 POZZONI, LUCA EZIO
Precision vs. efficiency: a bit-level variable-length floating-point approach to neural network quantization
2022/2023 GHIELMETTI, NICOLÒ
Pthread implementation in PandA
2018/2019 BINETTI, RICCARDO
A system-on-chip platform for the protection of on-chip communications
2020/2021 TIBALDI, MATTIA
Trace-based automated logical debugging for high-level synthesis generated circuits
2015/2016 CASTELLANA, MICHELE
Trimming the bit : optimizing high-level synthesis of floating-point based descriptions by extending value range analysis
2018/2019 FIORITO, MICHELE
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