This thesis has as objective the realization of base hardware and software for the characterization of the ASIC MARC, a low noise integrated front-end for the fast reading of high performance scientific CCDs developed at the Lawrence Berkeley National Laboratory (LBNL). The proposed front end aims to improve the frame-rate, speeding up the electronic processing time, through the use of the current readout approach. This approach, is already being used successfully for other types of detectors including DEPFET (DEpleted P-channel Field Effect Transistor), and it is potentially able to overcome the intrinsic limits of the most common voltage readout of the CCDs in configuration source-follower. The ASIC MARC is a time-varying filter that implements a trapezoidal weight function through the switched-current technique (SCT), by means of which are performed two correlated measures of currents offset and offset plus the signal incoming in the filter, with the purpose of providing amplification only on the signal of the detector. Starting from the specifications of the front-end and the LBNL CCD it has therefore been developed an experimental setup that configures and generates the signals useful to control both devices (CCD, MARC). The setup is constituited of a digital core control based on a Xilinx Spartan 6 and four printed circuits dedicated to filtering and amplification of the signals from and toward the CCD and the ASIC. It also includes a section for the generation of the phases clocks of the detector. The experimental measurements performed on the ASIC MARC have revealed excellent characteristics of linearity and weight functions of the front-end. From these can be deduced an error of subtraction of the offset current less than 1% for all the processing times considered, while the non-linearity of the filter are kept below 0.3% for all gains and at the lowest expected processing time of 300 ns, equivalent to a frame-rate of 400 fps, assuming operate the CCD with the same timing proposed by the manufacturer. The preliminary measurements of noise, although slightly worse in comparison to the result of simulations, are significantly better than that ones obtained with the circuit solutions currently present for the same sensor.
Questa tesi ha come obiettivo la realizzazione di una piattaforma hardware e software per la caratterizzazione dell’ASIC MARC, un front-end integrato a basso rumore per la lettura veloce di CCD scientifici ad alte prestazioni sviluppati presso i Lawrence Berkeley National Laboratory (LBNL). Il front-end si propone di ottimizzarne il framerate velocizzando il tempo di processamento elettronico, mediante l’impiego del current readout approach. Tale approccio di lettura, già impiegato con successo per altre tipologie di detector tra cui i DEPFET (DEpleted P-channel Field Effect Transistor), è potenzialmente in grado di superare i limiti intrinseci della più comune lettura in tensione dei CCD. L’ASIC MARC è un filtro tempo-variante che implementa una funzione peso trapezoidale mediante la tecnica switched-current (SCT), con la quale vengono eseguite due misure correlate delle correnti di offset e offset più segnale entranti nel filtro allo scopo di amplificare il solo segnale del rivelatore. A partire dalle specifiche del front-end e del LBNL CCD è stato quindi sviluppato un setup sperimentale per configurare e generare i segnali utili al controllo di entrambi i dispositivi (CCD, MARC). Il setup è costituito da un core di controllo digitale basato su una FPGA Spartan6 e da circuiti stampati dedicati a filtraggio ed amplificazione dei segnali da e verso il CCD e l’ASIC. Esso include inoltre sezioni digitali per la generazione dei clock di comando delle fasi del detector. Le misure sperimentali effettuate hanno messo in luce ottime caratteristiche di linearità e funzioni peso del front-end. Da queste ultime si deduce un errore di sottrazione dell’offset in corrente inferiore all’1% per tutti i tempi di processamento considerati mentre le non linearità del filtro si mantengono al di sotto dello 0.3% per tutti i guadagni ed al minor tempo di processamento previsto di 300 ns, equivalente ad un frame-rate di 400 fps nell’ipotesi di operare il CCD con lo stesso timing proposto dal costruttore. Le misure preliminari di rumore, sebbene leggermente peggiori rispetto al frutto delle simulazioni, risultano significativamente migliori di quanto ottenuto dalle soluzioni circuitali ottime attualmente presenti per il medesimo sensore.
Caratterizzazione di un front-end a basso rumore per la lettura in corrente di fotorivelatori CCD
LAZZARI, FABIO
2013/2014
Abstract
This thesis has as objective the realization of base hardware and software for the characterization of the ASIC MARC, a low noise integrated front-end for the fast reading of high performance scientific CCDs developed at the Lawrence Berkeley National Laboratory (LBNL). The proposed front end aims to improve the frame-rate, speeding up the electronic processing time, through the use of the current readout approach. This approach, is already being used successfully for other types of detectors including DEPFET (DEpleted P-channel Field Effect Transistor), and it is potentially able to overcome the intrinsic limits of the most common voltage readout of the CCDs in configuration source-follower. The ASIC MARC is a time-varying filter that implements a trapezoidal weight function through the switched-current technique (SCT), by means of which are performed two correlated measures of currents offset and offset plus the signal incoming in the filter, with the purpose of providing amplification only on the signal of the detector. Starting from the specifications of the front-end and the LBNL CCD it has therefore been developed an experimental setup that configures and generates the signals useful to control both devices (CCD, MARC). The setup is constituited of a digital core control based on a Xilinx Spartan 6 and four printed circuits dedicated to filtering and amplification of the signals from and toward the CCD and the ASIC. It also includes a section for the generation of the phases clocks of the detector. The experimental measurements performed on the ASIC MARC have revealed excellent characteristics of linearity and weight functions of the front-end. From these can be deduced an error of subtraction of the offset current less than 1% for all the processing times considered, while the non-linearity of the filter are kept below 0.3% for all gains and at the lowest expected processing time of 300 ns, equivalent to a frame-rate of 400 fps, assuming operate the CCD with the same timing proposed by the manufacturer. The preliminary measurements of noise, although slightly worse in comparison to the result of simulations, are significantly better than that ones obtained with the circuit solutions currently present for the same sensor.File | Dimensione | Formato | |
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2015_02_Lazzari.pdf
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https://hdl.handle.net/10589/103330