A power gating methodology to aggressively reduce leakage power in networks-on-chip buffers

Buffers are the major leakage component in multi-cores which relies on NoC and also they affect heavily the performance of the whole interconnect and the system. Traditionally they are used for the worst traffic scenario, thus they remain idle or underutilized for the majority of the time. The under use of these resourced is magnified by the burst traffic behavior in real applications, where high traffic periods are alternated with periods where there is no traffic. The problem to mitigate leakage power is considered in many methodologies by the exploitation of the power gating actuator both at router or buffer level. However the power gating actuation at router level is a suitable technique against low and medium traffic while it is useless at high traffic. Moreover they impose strong constraints to the router function and the network topology. This thesis presents a power gating methodology focusing on the router's buffers in NoC based multi-cores to reduce leakage power while keeping almost the same performance of the baseline considered NoC. The methodology is aseptic from the routing scheme or the topology of the network and it focuses also on the minimization of power on and off oscillations, introducing traffic reshaping. Furthermore it does not impact in any way on the critical path of the NoC router. Results obtained with synthetic traffic and real applications with up to 64 cores systems show a limited performance overhead of at most the 2% on average introduced by the methodology, with a per router energy saving of up to 74%.