The aim of my thesis work was to design smart pixels in 0.18 µm BCD technology and characterize analog silicon photomultiplier (SiPM) fabricated in 0.35 µm. Both single photon arrays (SPAs) and digital SiPMs are based on Single Photon Avalanche Diodes (SPADs), which are p-n junction reverse biased above the breakdown voltage (the voltage that exceed the breakdown is called excess voltage), which provide a macroscopic current pulse when a photon impinges on their active area. The pixels that compose a SPA work independently of each other, and they include a SPAD, a quenching circuit and digital electronics such as counters, Time to Digital Converters (TDCs), small memories, output bu ers, etc. Instead a dSiPM behaves like a single point detector and it is implemented using only a SPAD and a quenching circuit as microcell. The rst part of the work was the design of the basic digital front-end circuit for the SPAD: the quenching circuit. This integrated front-end provides a digital stabilized pulse, every time an avalanche is triggered, and the control logic quenches and reactivates the sensor after a user adjustable \hold-o " time. The rst developed circuits implemented were state-of-art topologies of quenching circuit, designed for CMOS technology. For the rst time I integrated them in a BCD technology, in order to understand the issues of this new technology, and thus collect useful information for the second design process. Exploiting the DMOS available in BCD technology I also designed new quenching circuits able to work at excess voltages up to 10 V. The second part of the work was to develop new quenching topologies to be used in gated mode SPAs. In some applications it is useful to turn ON the SPADs only in well-de ned temporal windows, in order to avoid their saturation. The main strike was to nd a topology that permits the integration in large matrix of the smart pixels. Therefore, the design was focused on minimize the power consumption of the single pixel and maximize its ll factor. The last part of the work was dedicated to the characterization of the analog silicon multipliers previously developed by a research group of Politecnico di Milano and fabricated in a 0.35 µm CMOS technology. These sensors provide an output current proportional to the number of impinging photons. When a single photon is absorbed the current pulse has a rising edge in the order of few nanoseconds, thus wide bandwidth readout circuits have to be used. In particular, a transimpedance ampli er was used to characterize the multiphoton response and the timing performance of the SiPMs. The transimpedance ampli er was simulated with PSpice, in order to properly compensate it. The results obtained from the characterization will be exploited for the design of new analog and digital SiPMs in BCD technology.
Per il lavoro di tesi ho progettato un nuovo tipo di smart pixel in tecnologia 0.18 µm BCD e in seguito ho caratterizzato un SiPM analogico progettato e prodotto a 0.35 µm HV-CMOS. Lo SPAD (Single Photon Avalanche Diode) e l'elemento fondamentale degli array a singolo fotone (SPAs) e dei fotomoltiplicatori in silicio (SiPMs). Lo SPAD e una giunzione p-n polarizzata inversamente a una tensione maggiore della tensione di breakdown. Il valore di tensione che eccede il breakdown, e chiamata tensione di excess. Questi particolari dispositivi vengono attraversati da una corrente macroscopica ogni qual volta un fotone incide sull'area attiva. I pixel che compongono una camera a singolo fotone, lavorano indipendentemente fra loro, e si compongono di uno SPAD, un circuito di quenching e elettronica digitale ausiliaria (contatori, time to digital converters, piccolo memorie, bu er di uscita etc.). Un SiPM digitale si comporta come un sensore a singolo pixel, con una grande area attiva, e si compone di pixel formati solo da SPAD e circuiti di \quenching". Nella prima parte del lavoro ho progettato il front-end digitale dello SPAD: il circuito di quenching. Questo front-end genera un segnale digitale, ogni volta che una moltiplicazione a valanga viene innescata nello SPAD; la logica di controlla spegne la valanga, e riattiva il sensore dopo un tempo regolabile dall'esterno (hold-o ). I primi circuiti progettati, rappresentano lo stato dell'arte dei circuiti di quenching, progettati in tecnologia CMOS. Per la prima volta, li ho integrati in tecnologia BCD, cos da poter capire i problemi di questa nuova tecnologia, e raccogliere informazioni essenziali per la seconda fase di progetto. Utilizzando i DMOS della tecnologia BCD ho progettato dei nuovi circuiti di quenching da essere utilizzati a tensioni di excess no a 10 V. Per la seconda parte del lavoro di tesi, ho progettato dei circuiti di quenching per array a singolo fotone e fotomoltiplicatori digitali in modalit a \gated". Per alcune applicazioni e necessario accendere lo SPAD, solo in un periodo di tempo ben de nito, cos da evitarne la saturazione. L'obiettivo era trovare una topologia, che potesse essere integrata in grandi matrici. Per la progettazione dei nuovi \smart pixel", perci o, ci si e focalizzati sul minimizzare la potenza consumata e massimizzare il ll factor. In ne, per l'ultima parte del mio lavoro, mi sono dedicato alla caratterizzazione di fotomoltiplicatori analogici in silicio, progettati nello SPADlab del Politecnico di Milano, in tecnologia 0.35 µm HV-CMOS. Questi sensori generano una corrente macroscopica, proporzionale al numero di fotoni incidenti sull'area attiva. Quando un fotone innesca una moltiplicazione a valanga, l'impulso di corrente ha un fronte di salita nell'ordine di pochi nanosecondi; per questo e necessario progettare ed utilizzare stadi di lettura a ampia banda. In particolare, e stato utilizzato un transimpedenza per caratterizzare la risposta a fotoni multipli e le prestazioni in termini di risposta temporale del dispositivo. Il transimpedenza e stato simulato e conseguentemente compensato con PSpice. I risultati ottenuti dalla caratterizzazione serviranno a progettare nuovi SiPM, sia digitali che analogici, in tecnologia BCD.
Front-end circuits for single photon arrays and digital SiPMs in BCD technology
SARTIANO, DEMETRIO
2015/2016
Abstract
The aim of my thesis work was to design smart pixels in 0.18 µm BCD technology and characterize analog silicon photomultiplier (SiPM) fabricated in 0.35 µm. Both single photon arrays (SPAs) and digital SiPMs are based on Single Photon Avalanche Diodes (SPADs), which are p-n junction reverse biased above the breakdown voltage (the voltage that exceed the breakdown is called excess voltage), which provide a macroscopic current pulse when a photon impinges on their active area. The pixels that compose a SPA work independently of each other, and they include a SPAD, a quenching circuit and digital electronics such as counters, Time to Digital Converters (TDCs), small memories, output bu ers, etc. Instead a dSiPM behaves like a single point detector and it is implemented using only a SPAD and a quenching circuit as microcell. The rst part of the work was the design of the basic digital front-end circuit for the SPAD: the quenching circuit. This integrated front-end provides a digital stabilized pulse, every time an avalanche is triggered, and the control logic quenches and reactivates the sensor after a user adjustable \hold-o " time. The rst developed circuits implemented were state-of-art topologies of quenching circuit, designed for CMOS technology. For the rst time I integrated them in a BCD technology, in order to understand the issues of this new technology, and thus collect useful information for the second design process. Exploiting the DMOS available in BCD technology I also designed new quenching circuits able to work at excess voltages up to 10 V. The second part of the work was to develop new quenching topologies to be used in gated mode SPAs. In some applications it is useful to turn ON the SPADs only in well-de ned temporal windows, in order to avoid their saturation. The main strike was to nd a topology that permits the integration in large matrix of the smart pixels. Therefore, the design was focused on minimize the power consumption of the single pixel and maximize its ll factor. The last part of the work was dedicated to the characterization of the analog silicon multipliers previously developed by a research group of Politecnico di Milano and fabricated in a 0.35 µm CMOS technology. These sensors provide an output current proportional to the number of impinging photons. When a single photon is absorbed the current pulse has a rising edge in the order of few nanoseconds, thus wide bandwidth readout circuits have to be used. In particular, a transimpedance ampli er was used to characterize the multiphoton response and the timing performance of the SiPMs. The transimpedance ampli er was simulated with PSpice, in order to properly compensate it. The results obtained from the characterization will be exploited for the design of new analog and digital SiPMs in BCD technology.| File | Dimensione | Formato | |
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https://hdl.handle.net/10589/123925