Effect of interfacial stoichiometry and threading dislocation density on III-V Esaki diodes current characteristics

Tunnel field effect transistors (TFETs) are considered as a promising solution to substitute the current metal-oxide-semiconductor field-effect transistor (MOSFET) for low-power logic. The lower power consumption of TFETs is related to their sub-60 mV/dec subthreshold swings and the band-to-band tunneling mechanism for carrier transport. Currently, the main problem with TFETs is a high defect-assisted current in the off-state, which increases the power consumption. The correlation between the off current of a TFET and the defectivity of the material is still not clear and needs further investigation. This study focuses on the effect of interfacial stoichiometry and threading dislocation density (TDD) on the behavior of III-V InGaAs/GaAsSb and InAs/GaSb heterojunctions for TFET application. In order to facilitate both the processing and the data analysis, heterojunction Esaki diodes are studied. The first part of this work focuses on the process flow used to fabricate these diodes. A novel process flow with Al2O3 sidewall passivation is proposed to passivate sidewall defects. InGaAs homojunction diodes are fabricated using a reference flow previously developed at imec, and this newly developed process flow. The results are compared to literature, and the novel process flow is found to be unreliable due to nonuniformities in the Al2O3 layer. The second part of this work focuses on the effect of interfacial stoichiometry in InGaAs/GaAsSb and InAs/GaSb heterostructures. Both heterostructures are fabricated with a InSb or GaAs interfacial stoichiometry. For the InGaAs/GaAsSb heterostructure, it is found that the interfacial stoichiometry does not influence the roughness of the samples or the I-V characteristics of diodes. Therefore we cannot make a recommendation for the interface stoichiometry of InGaAs/GaAsSb TFETs. For the InAs/GaSb heterostructure, the sample with a GaAs interfacial stoichiometry has a higher TDD and roughness with respect to the sample with a InSb interfacial stoichiometry. Also, the diodes with GaAs interface do not show any negative differential resistance (NDR), while the diodes with InSb interface present weak NDR, which is confirmed by low temperature measurements. Based on this result, is it recommended to fabricate InAs/GaSb TFETs with a InSb interface instead of a GaAs interface. In the third part, the effect of TDD is investigated on InAs/GaSb heterojunctions grown on three different substrates: GaSb, GaAs and Si. Diodes on the lattice matched GaSb and lattice mismatched GaAs substrates are measured at 77K and present NDR. However it is not possible to correlate the I-V characteristics with TDD, because the contact to the p-type material is placed at the back side of the substrate. Therefore the substrate influences the diffusion current, which in turn masks the excess current related to TDD. The InAs/GaSb heterostructure on silicon presented anomalous values of current, which are attributed to problems with the process flow. It is recommended to repeat this experiment with an modified process flow and optimized contacts.