Reconfigurable architectures have become one of the key implementation platforms for digital circuits in many different application areas. Although FPGAs progressively changed from homogeneous architectures containing identical logic cells to heterogeneous architectures comprising different types of cells (CLB, BRAM, DSP, etc.), the structure itself is still regular and piecewise homogeneous. The regularity of resources found in FPGAs is a unique feature and are utilized in timing critical application, such as time-to-digital converters, where the regularity of the routing structure is used to measure the time difference between two electrical pulses with the precision of picoseconds. Another application domain, which exploits the regularity of the FPGA resources, is partially reconfigurable systems, where hardware modules can be placed at positions with the same resource arrangement they are built from. Thus, the regularity of the partially reconfigurable region increases the flexibility for the placement of the modules. The existing tools utilize the regularity of the FPGA by implementing repeated design patterns using the same types of resources and wires. The necessary regularity of the designs is achieved by a manual place and route, which is a tedious and error-prone process. Current commercially available FPGA place and route tools are lacking an option for generating these types of regular designs. In this thesis a novel design flow called Design flow for Homogeneous Hard Macros (DHHarMa) is presented, which automatically generates homogeneous hard macros for Xilinx FPGAs starting from a high-level description, such as VHDL or Verilog. This gives the designer the ability to quickly create or modify designs, which require being homogeneously placed and routed. The core components of the design flow are a homogeneous packer, placer and router, which as a result generate a regular structured design based on a user-defined FPGA partitioning. The main work of this thesis is focused on the DHharMa Router, presenting a novel homogeneous router for hard macro. The issues related to the homogeneity in the routing phase are analysed, considering the advantages of a homogeneous approach. Afterwards, a detailed logic and implementation of this router is presented, providing a useful contribution on the partial dynamic reconfiguration of the FPGAs. The design flow currently supports Xilinx Virtex-4, -5, -6 and Spartan-6 FPGA families. The place and route tools use a resource library that is automatically generated for the target FPGA family by extracting relevant information from the vendor tools. The tool chain is demonstrated for the design of hard macros for a time-to-digital converter and a tiled partially reconfigurable region. The resulting designs are evaluated with respect to resource requirements and timing constraints. The major contribution of this thesis concern a homogeneous router algorithm, which ensures identical routing within predefined regions. Moreover, the same routing logic is suitable for different types of FPGAs (Xilinx Virtex-4, -5, -6 and Spartan-6 FPGA families). The minor contribution provide is in the homogeneous packer and placer of the DHHarMa flow, which ensure identical placement of resources within predefined regions. Beyond, the thesis gives useful information about the Xilinx FGPAs architecture, and a resource database (logic cells, wires, PIPs, etc.) for Virtex-4, -5, -6 and Spartan-6 FPGA families is presented. Chapter 1 introduces the thesis works, providing the problem definition and the overviews of the DHHarMa design flow. The achitectures of the considered Xilinx FPGAs are presented in Chapter 2. Moreover a detailed analysis of FPGA routing system is given. The Chapter 3 provides the necessary concepts in order to understand the development of the design flow, in particular the communication infrastructure information and the Xilinx Design Language (XDL). Afterwards, in Chapter 4 are presented motivations of the thesis work, comparing it with the existing state of art. The novel DHHarMa flow is presented in deep in Chapter 5, which the flow is analysed in its single parts (packer, placer and router). The Chapter 6 gives a detailed explanation of the routing algorithm; in particular a new routing logic which considers homogeneity in the design flow is shown. The results of the entire flow and of the router algorithm, compared with the Xilinx tools, are in the Chapter 7. At the end, in Chapter 8 are discussed the results of the presented approach, considering the possible future works related to this thesis.
Le architetture riconfigurabili si sono rivelate di notevole importanza nella implementazione di circuiti digitali in vari campi applicativi. Bench´e la struttura delle FPGAs (Field Programmable Gate Array) progressivamente sia cambiata, passando da un’architettura omogenea con identica logica, a un’architettura di tipo eterogeneo comprendendo diverse componenti logiche (CLB, BRAM, DSP, etc.), la struttura risulta ad ogni modo regolare e a tratti omogenea. Questo tipo di regolarit` a all’interno delle FPGAs `e una caratteristica unica ed `e utilizzata, ad esempio, in convertitori time-to-digital, dove la regolarit`a della struttura di routing `e usata per misurare le differenze tra due pulsazioni elettriche, con precisione intorno al picosecondo. Un altro dominio applicativo, che sfrutta la regolarit`a delle risorse nelle FPGAs, riguarda i sistemi parzialmente riconfigurabili, dove i moduli hardware possono essere piazzati in diverse posizioni, i quali presentano la stessa disposizione di risorse. Perci`o, i sistemi parzialmente riconfigurabili utilizzano la regolarit`a della periferica, incrementando la flessibilit`a del piazzamento dei moduli. Gli strumenti sviluppati fino ad ora, i quali sfruttano la regolarit`a delle FPGAs, implementando ripetutamente porzioni di logica, utilizzando lo stesso tipo di risorse e routing. La regolarit`a necessaria del design `e raggiunta con un place and route effettuato manualmente, metodo che risulta lungo e tendenzialmente ha un tasso elevato di errore. I prodotti commerciali attualmente sul mercato, non permettono di eseguire questi tipi regolari di design. In questa tesi, un nuovo flusso di design chiamato Design flow for Homogeneous Hard Macros (DHHarMa) `e presentato, il quale genera automaticamente hard macro di tipo omogeneo per Xilinx FPGAs, partendo da un linguaggio ad alto livello, ad esempio VHDL o Verilog. Questa importante caratteristica fornisce al progettista la possibilit`a di creare e modificare quei tipi di design, i quali richiedono di essere omogeneamente placed and routed. Le componenti chiave del flusso presentato, sono un omogeneo packer, placer and router, le quali come risultato, forniscono una struttura regolare basata su una partizione definita dall’utente. Il lavoro principale di questa tesi `e concentrato sul DHHarMa Router, presentando un innovativo router di tipo omogeneo per hard macro. Le problematiche riguardanti questa fase del flusso sono analizzate, considerando i vantaggi di un approccio di tipo omogeneo. In seguito, `e presentata la logica e l’implementazione del router, fornendo un importante contributo per quanto riguarda i sistemi parzialmente riconfigurabili per FPGAs. Il flusso di progetto attualmente supporta i seguenti tipi di Xilinx FPGA: Virtex-4, -5, -6 and Spartan-6. Gli strumenti di place and route usano opportune librerie che automaticamente sono generate per le FPGA considerate, estraendo informazioni fornite dagli strumenti forniti dal produttore. Il flusso `e presentato nei casi di design di hard macros per convertitori time-to-digital e per sistemi parzialmente riconfigurabili di tipo Tile Partitioned. I risultati dei design sono valutati considerando risorse occupate e timeing. Il maggior contributo fornito in questa tesi riguarda la presentazione di un algoritmo di routing omogeneo, il quale assicura un identico routing all’interno di regioni predefinite. La logica di routing presentata `e applicabile allo stesso modo su varie tipologie di FPGAs (Xilinx Virtex-4, -5, -6 and Spartan-6 FPGA families). I contributi minori riguardano le parti di packer e placer del flusso DHHarMa, i quali assicurano un piazzamento di risorse in regioni predefinite. Inoltre, la tesi fornisce informazioni che interessano l’architettura delle FPGAs e un database delle risorse (logic cells, wires, PIPs, etc.) per le famiglie Virtex-4, -5, -6 and Spartan-6. Il Capitolo 1 introduce il lavoro di tesi, fornendo la definizione del problema e una visione d’insieme del flusso DHHarMa. L’architettura delle FPGAs considerate `e presentata nel Capitolo 2. Inoltre, `e fornita un’analisi dettagliata del sistema di routing per le famiglie di FPGAs studiate. Il Capitolo 3 fornisce i concetti necessari per comprendere il flusso di design presentato (infrastrutture di comunicazione e Xilinx Design Language). In seguito, nel Capitolo 4, sono presentate le motivazioni del lavoro di tesi, confrontando il flusso presentato rispetto allo stato dell’arte. DHHarMa `e presentato nel dettaglio nel Capitolo 5, nel quale il flusso `e analizzato nel dettaglio nelle sue single parti (packer, placer and router). Il Capitolo 6 fornisce una dettagliata esposizione dell’algoritmo di routing, in particolare viene presentato come un routing omogeneo pu`o essere eseguito. I risultati del flusso DHHarMa e del router omogeneo, forniti nel Capitolo 7, sono comparati con gli strumenti forniti da Xilinx. Infine nel Capitolo 8 i risultati del lavoro di tesi sono commentati, considerando i suoi possibili sviluppi futuri.
Homogeneous Communication Router for Xilinx FPGAs
COZZI, DARIO
2009/2010
Abstract
Reconfigurable architectures have become one of the key implementation platforms for digital circuits in many different application areas. Although FPGAs progressively changed from homogeneous architectures containing identical logic cells to heterogeneous architectures comprising different types of cells (CLB, BRAM, DSP, etc.), the structure itself is still regular and piecewise homogeneous. The regularity of resources found in FPGAs is a unique feature and are utilized in timing critical application, such as time-to-digital converters, where the regularity of the routing structure is used to measure the time difference between two electrical pulses with the precision of picoseconds. Another application domain, which exploits the regularity of the FPGA resources, is partially reconfigurable systems, where hardware modules can be placed at positions with the same resource arrangement they are built from. Thus, the regularity of the partially reconfigurable region increases the flexibility for the placement of the modules. The existing tools utilize the regularity of the FPGA by implementing repeated design patterns using the same types of resources and wires. The necessary regularity of the designs is achieved by a manual place and route, which is a tedious and error-prone process. Current commercially available FPGA place and route tools are lacking an option for generating these types of regular designs. In this thesis a novel design flow called Design flow for Homogeneous Hard Macros (DHHarMa) is presented, which automatically generates homogeneous hard macros for Xilinx FPGAs starting from a high-level description, such as VHDL or Verilog. This gives the designer the ability to quickly create or modify designs, which require being homogeneously placed and routed. The core components of the design flow are a homogeneous packer, placer and router, which as a result generate a regular structured design based on a user-defined FPGA partitioning. The main work of this thesis is focused on the DHharMa Router, presenting a novel homogeneous router for hard macro. The issues related to the homogeneity in the routing phase are analysed, considering the advantages of a homogeneous approach. Afterwards, a detailed logic and implementation of this router is presented, providing a useful contribution on the partial dynamic reconfiguration of the FPGAs. The design flow currently supports Xilinx Virtex-4, -5, -6 and Spartan-6 FPGA families. The place and route tools use a resource library that is automatically generated for the target FPGA family by extracting relevant information from the vendor tools. The tool chain is demonstrated for the design of hard macros for a time-to-digital converter and a tiled partially reconfigurable region. The resulting designs are evaluated with respect to resource requirements and timing constraints. The major contribution of this thesis concern a homogeneous router algorithm, which ensures identical routing within predefined regions. Moreover, the same routing logic is suitable for different types of FPGAs (Xilinx Virtex-4, -5, -6 and Spartan-6 FPGA families). The minor contribution provide is in the homogeneous packer and placer of the DHHarMa flow, which ensure identical placement of resources within predefined regions. Beyond, the thesis gives useful information about the Xilinx FGPAs architecture, and a resource database (logic cells, wires, PIPs, etc.) for Virtex-4, -5, -6 and Spartan-6 FPGA families is presented. Chapter 1 introduces the thesis works, providing the problem definition and the overviews of the DHHarMa design flow. The achitectures of the considered Xilinx FPGAs are presented in Chapter 2. Moreover a detailed analysis of FPGA routing system is given. The Chapter 3 provides the necessary concepts in order to understand the development of the design flow, in particular the communication infrastructure information and the Xilinx Design Language (XDL). Afterwards, in Chapter 4 are presented motivations of the thesis work, comparing it with the existing state of art. The novel DHHarMa flow is presented in deep in Chapter 5, which the flow is analysed in its single parts (packer, placer and router). The Chapter 6 gives a detailed explanation of the routing algorithm; in particular a new routing logic which considers homogeneity in the design flow is shown. The results of the entire flow and of the router algorithm, compared with the Xilinx tools, are in the Chapter 7. At the end, in Chapter 8 are discussed the results of the presented approach, considering the possible future works related to this thesis.| File | Dimensione | Formato | |
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2011_03_Cozzi.pdf
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Descrizione: Testo della tesi
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https://hdl.handle.net/10589/12964