Nanofabrication and characterization of high performance transistors based on CVD graphene and hBN/graphene/hBN heterostructures

Two-dimensional materials, such as graphene, MoS2 or WSe2, represent a new paradigm in the thin- film transistor technology, providing also the opportunity for new device concepts. Graphene is one of the possible contenders in high frequency electronics, mainly due to its high charge carrier mobility and velocity saturation, which exceed that of conventional high mobility semiconductors (III-V or SiGe). Scalable production techniques, such as chemical vapour deposition (CVD), can now deliver graphene on a large scale which is interesting from the industrial point of view. However, fabrication of graphene fi eld-eff ect transistors (GFETs) needs further development if graphene is to compete with established semiconductor technologies. One of the main parameters degrading high-frequency response of GFETs is contact resistance, which should be reduced below 100 Ohmµm to reach that of conventional high-frequency transistors. During my PhD studies I successfully demonstrated graphene/metal contacts with a typical contact resistance below 80 Ohmµm at the Dirac point. The contact resistance was determined by transmission line measurements (TLMs) at room temperature. The low contact resistance was obtained by etching holes in CVD-grown graphene channel before the deposition of contacts. This increases the contact edge lenght with metal contacts deposited on top and therefore the injection of carriers through graphene edges. Such ultra-low contact resistance is comparable to that of InP THz transistors and provides a viable route to high-frequency GFETs. The benefi ts and improvements in graphene technology were tested through the fabrication and characterization of high frequency GFETs: I designed and fabricated these devices using CVD grown graphene as a channel material transferred on a 1 µm thick SiO2 substrate. Di fferent materials and designs were electrically tested: we used AlOx as a top gate dielectric in all transistors while changing the metal contacts and layouts. We obtained the record high fmax/fT in GFETs, demonstrating that graphene transistor technology can compete with well-established technologies. Here, fmax is the maximum frequency of oscillation and fT is the cutoff frequency. In order to further improve the frequency response of the GFETs I investigated alternative thin gate oxides, such as TiOx and HfOx, because they have very large dielectric constants. To this end, graphene inverters were realized in which the lowest contact resistance obtained previously was implemented. Due to a lack of a proper growing method, HfOx did not provide any bene ts while TiOx provided interesting and promising results. However, high leakage currents in GFETs with TiOx gate oxide require further investigations which should open a path to further improvements. One of the main limitations of graphene in technological applications is the reduction of its mobility exhibited in realistic devices. As exfoliated, graphene does not have the high mobility which is theoretically predicted. For this reason, I then studied alternative substrates for GFETs which should increase mobility by suppressing the substrate induced scattering. First, I focused on STO (strontium titanate) as a high-k substrate/gate oxide for graphene (140 nm crystalline STO layer was grown on top of a conductive LSMO layer). I fabricated and characterized GFETs and graphene inverters on such substrates. Maximum transconductance around 600 µS/µm and DC voltage gain around 5 at a gate length of 2 µm were obtained, showing good electronic properties of GFETs fabricated on STO substrates. However, since mobility in these GFETs was still very low and gate leakage currents high, research on another type of substrate, namely hBN (hexagonal boron nitride) was initiated. Research on hBN substrates led to very preliminary but interesting results which need further investigations. The bene ts of this material as a substrate for graphene have been widely demonstrated in literature, but not in more complex graphene devices and circuits. Further improvements in this research fi eld were attained during the period I spent in the Nanocarbon Group of the Denmark Technical University, Copenhagen, where my research was focused on the fabrication and characterization of Van der Waals heterostructures of graphene and hBN. Thanks to the stacking technique developed in this group, I developed my own procedure capable of realizing hBN/graphene/hBN heterostructures in which the thickness of the top hBN layer was below 8 nm, preserving at the same time the improvement of the electrical properties provided by such encapsulation. Both Raman and electrical characterizations were performed on these devices, first for a pre-selection of the high-quality areas for the fabrication of final devices and second to link the optical and electronic properties as a test of the technological improvements. The heterostructures were electrically characterized, from room to cryogenic temperatures (4 K). Another achieved objective was the large obtained quantity (and quality) of doping-homogeneous stacks (doping concentration < 10^12 cm^-2) with large mobility of graphene (25000 cm^2V^-1s^-1 at room temperature) and with a very thin top hBN. With thicker top hBN, I consistently obtained graphene mobilities between 30000 and 50000 cm^2V^-1s^-1 (at room temperature), which were measured by the Van der Pauw method. This refl ects the method optimizations I performed, leading to a more stable technology (for the graphene encapsulation) and to more scalable fabrication. From a technological point of view, these fi rst studies on thin hBN are quite interesting and important because the implementation of thin hBN as a top gate insulator is one of the main goals of the state-of-the-art graphene electronics. We also observed high leakage currents through thin top hBN gates at room temperature. Comparing to other studies, we discovered that it is possible to have defect mediated temperature-dependent leakage currents through a low number of hBN layers. We therefore demonstrated that it is not possible to use hBN thinner than 10 nm as a thin top gate insulator at room temperature, because such layers have leakage resistance 100 MOhm. We also found that leakage currents decrease when temperature decreases, resulting in good gate insulation only at cryogenic temperatures. The presented studies open path to new research projects. From a graphene electronics point of view, the future ideas are to implement these developments in the realization of more complex electronic devices and circuits, such as graphene inverters and ring oscillators. The purpose is to increase performances of already demonstrated devices by replacing CVD graphene (channel material) with high-mobility encapsulated graphene and using hBN as a top gate insulator (with some additions of AlOx on top of hBN to prevent leakage currents). This also implies other studies, for example of contact resistance, which is now incompatible with the requirements for high frequency transistor operation. Finally, these studies should allow better understanding of required improvements of graphene high-frequency devices, both from a technological and fundamental point of view.