Advanced methods techniques and digital architectures for high performance timing of events

The precise measurement of time intervals is a primary goal in a growing number of applications and the challenge to achieve increasingly higher res- olutions than ever is a main topic of research. In this sense, Time–of–Flight measurements and Time–Correlated Photon Counting are two milestones. Since the intrinsic resolution of the sensors used today is in the order of tens of picoseconds, the measurement systems must guarantee performance at least of this order. The choice of making digital a part or the totality of the measurement elec- tronic systems exploits well–known advantages from the adaptivity, to the versatile calibration, to the easiness of implementation of powerful process- ing algorithms with lower power consumption, and area occupation with respect to the equivalent analog solutions. Historically, the well–established method for high–accuracy time interval measurements is the Time–to–Amplitude Conversion (TAC). However, nowa- days the Time–to–Digital Converter (TDC) is the landmark for determining the time instants at which digital events take place, also because it is the building block of Time–Mode circuits. As well known, these circuits code in- formation by the difference between the time instants at which digital events take place rather than the nodal voltages or branch currents of networks. The crucial issue is that Time–Mode circuits benefits at most from technol- ogy scaling. In fact, the improved switching characteristics of MOS transis- tors offer excellent timing accuracy such that the time resolution of digital circuits decisively surpasses the resolution of analog ones implemented in nodes of nm order. Moreover, there is a substantial reduction of power con- sumption as well as of area occupation. The fully digital architecture of the TDCs permits the use of signals that are discretized in only two logic levels. In relation with Voltage–Mode and Current–Mode analog approaches, this quantization makes the dynamic range of signals, defined as the maximum pulse time width, not dependent on the voltage scaling. The last generation of digital programmable devices as Field Programmable Gate Arrays (FPGAs) and System–of–Chips (SoCs) has made possible the implementation of high–accuracy TDC architectures on programmable logic with performance comparable with ASIC realizations. In this way, all the well–known advantages of using programmable devices are exploited, such as totally tunable characteristics, easiness of portability, reduced time–to–mar- ket, lower migration cost from one generation of technology to another, just to name a few. This has to be done always keeping on foreground the maximum functional performance. In the presented work, first five Chapters focus on the state–of–art tech- niques for implementing standard TDC architectures in programmable logic. Next, six and seven Chapters, introduce structural improvements in TDC architectures for achieving time accuracy comparable with that of equiv- alent ASIC solutions. It must be kept on the foreground that the logic that constitutes the heart of the TDC is asynchronous. In the specific, the dissertation inside Chapter four focuses on the maximization of sets of figures of merit single or grouped (precision, accuracy, resolution, power dissipation, area occupancy) depending on the target application. This is accomplished through measurement techniques like interpolation (Chapter 5) and sub–interpolation algorithms (Chapter 6) and their correspondent implementations (Chapter 7), among which a high–performance totally new solution called Super Wave Union sub–interpolation is presented. Moreover, all investigated issues have been simulated and experimentally validated on a wide spectrum of devices provided by the major producers of programmable logic devices, i.e. Xilinx and Altera. In this regard, in Chapter eight, all considered architectural issues of TDCs in FPGAs have been revisited from the perspective of the migration of the implementation firmware among different devices, by providing pre- cise guidelines for the realization of TDC IP–Cores. In Chapter 9 a hard- ware/firmware/software bundle based on an optimized TDC IP–Core is pre- sented and characterized in term of resolution, precision, dynamic range, linearity, temperature behavior, and acquisition rate. Finally, Chapter 10 reviews some examples of international scientific collab- orations where several ideas and implementation solutions proposed in this work have been put in play in real experimental environments.

The precise measurement of time intervals is a primary goal in a growing number of applications and the challenge to achieve increasingly higher resolutions than ever is a main topic of research. In this sense, Time-of-Flight measurements and Time-Correlated Photon Counting are two milestones. Since the intrinsic resolution of the sensors used today is in the order of tens of picoseconds, the measurement systems must guarantee performance at least of this order. The choice of making digital a part or the totality of the measurement electronic systems exploits well-known advantages from the adaptivity, to the versatile calibration, to the easiness of implementation of powerful processing algorithms with lower power consumption, and area occupation with respect to the equivalent analog solutions. The last generation of digital programmable devices as Field Programmable Gate Arrays (FPGAs) and System-of-Chips (SoCs) has made possible the implementation of high-accuracy TDC architectures on programmable logic with performance comparable with ASIC realizations. In this way, all the well-known advantages of using programmable devices are exploited, such as totally tunable characteristics, easiness of portability, reduced time-to-market, lower migration cost from one generation of technology to another, just to name a few. This has to be done always keeping on foreground the maximum functional performance. The dissertation focuses on the maximization of sets of figures of merit single such as precision, resolution, full-scale range, power consumption, area occupancy, acquisition rate, depending on the target application. This is accomplished through measurement techniques like Nutt-interpolation and sub-interpolation algorithms, among which a high-performance totally new solution is presented in this dissertation. In particular, state-of-the-art of multi-channels sub-interpolated TDCs based on Tapped Delay-Line (TDL) and Nutt-interpolation are considered, both in terms of ideal and real features. Consequence of that is the introduction of a mathematical theory, new in literature, which explains and quantifies advantages and limits of this solution. Moreover, all investigated issues have been simulated and experimentally validated on a wide spectrum of devices from the Xilinx and Altera manufacturers. In this regard, the issue of migrating firmware between different devices has been studied by providing precise guidelines for the realization of TDC IP-Cores with timing performance comparable with ASIC solutions in the same technological node designed for being migrated between devices from the same or different manufacturers. As reference case study, is presented the implementation of a very high-performance (high-range, high-resolution and high-precision) multi-channel TDL-TDC (i.e. smart triggering of events, 16 channels, 12ps r.m.s. precision, 9.45s full-scale range with a resolution of 250fs) in devices of different manufacturers (i.e. Altera and Xilinx), paying particular attention to the migration of architectures in structurally very different devices This instrument is being used in several national (2) and international (5) research activities, among which a review of some as examples is presented. Moreover, the most significant achievements accomplished during the activity are attested by 39 international publications (8 on journal), of which 13 as first author and 1 single name submission.