Modern embedded systems has started to gain an increasing popularity since the advent of Internet of Things (IoT), thanks to the fact that IoT paradigm involves a capillary distribution of smart objects, which are responsible for collecting and sharing information over the internet, as well as interacting with the surrounding environment. Such large number of interconnected objects introduces a wide range of security risks, mostly due to their peculiar nature: indeed, differently from the common digital systems, they are strongly exposed to attacks led by someone having physical access to them, given the context in which they normally operate. This class of attacks, known as Side Channel Attack (SCA), exploits the intrinsic link between the computation and one or more physical parameters of the system itself: to this end, one of the most prominent source of information is the power consumption of the devices. Typically, the evaluation of the resistance of the system against this type of attacks is performed post-manufacturing. This scenario is far from ideal: indeed, if the device is found vulnerable and a fix is required, it is almost impossible to avoid an increase of the development costs and of the time to market. Moreover, it is worth noticing that implementing countermeasures against power attacks deteriorates parameters, such as performances and the energy consumption, which in IoT devices shall usually meet compelling requirements. It is thus crucial to introduce the concept of system security starting from the early phases of the design flow, so that it can be evaluated as all the other parameters that determine the goodness of the design. This thesis presents a design methodology for Field Programmable Gate Array, FPGA, one of the most promising technology for IoT applications, that extends the common design flow with functionalities required to correctly evaluate the vulnerabilities to power attacks. The proposed methodology leverages simulations on the design models available during all the stages of the design flow to extract the power traces which are essential for the evaluation of the security sensitive points during the computation. In particular, two specific design models, commonly adopted by the designer to validate the system behavior at design time, have been employed: the model available after the synthesis phase and the one ready after the implementation stage. A relevant part of the work has been dedicated to the analysis of the impact of employing such models and of the consequences they have on the effectiveness of the vulnerability assessment. The proposed methodology has been validated against a fully compliant OpenRisc 1000 implementation. The obtained results show that both the employed models are effective for the evaluation of the resistance of the system to power attacks, and that, increasing the detail level of the design description, does not automatically produces a better detection of the vulnerabilities.
A partire dalla nascita dell’Internet of Things (IoT), i sistemi embedded moderni hanno iniziato a godere di una popolarità crescente, grazie al fatto che tale paradigma prevede una distribuzione capillare di oggetti intelligenti incaricati di raccogliere, condividere informazioni attraverso internet e di interagire con l’ambiente circostante. Le proiezioni affermano che nell’anno 2022 si raggiungerà il numero di 29 miliardi di dispositivi IoT connessi ad internet. Un numero così elevato di sistemi interconnessi introduce un ampio spettro di rischi per la loro sicurezza, soprattutto a causa della loro peculiare natura: essi infatti, diversamente dai normali sistemi digitali, sono fortemente esposti ad attacchi condotti da chi ha accesso fisico al dispositivo, dato il contesto in cui si trovano normalmente ad operare. Questa classe di attacchi, nota con il nome di attacchi side-channel (SCAs), sfrutta il collegamento intrinseco tra la computazione effettuata dal sistema e alcuni parametri fisici del dispositivo stesso: una delle maggiori fonti di informazione, in questo senso, è costituita dal consumo di potenza. La valutazione della resistenza del sistema contro gli attacchi di questo tipo tipicamente avviene solo dopo la sua effettiva produzione. Questa situazione rappresenta una condizione tutt’altro che ideale: infatti, nel caso in cui il dispositivo risulti vulnerabile e vi si debba porre rimedio, un aggravio dei costi di sviluppo e un allungamento del time to market risultano pressoché inevitabili. Inoltre, è necessario considerare che l’implementazione delle eventuali contromisure deteriora parametri, come le prestazioni e l’energia richiesta dal sistema, che, nei dispositivi IoT, sono solitamente sottoposti a vincoli stringenti. È quindi di fondamentale importanza introdurre il concetto di sicurezza già a partire dalle prime fasi del flusso di progetto, affinché essa possa essere considerata al pari di tutti gli altri parametri che determinano la bontà del progetto. Questa tesi presenta una metodologia di sviluppo per Field Programmable Gate Array (FPGA), tecnologia molto promettente per applicazioni IoT, in grado di estendere il normale flusso di progetto con le funzionalità necessarie per una corretta analisi delle vulnerabilità agli attacchi che sfruttano il consumo di potenza come fonte di informazione. La metodologia proposta utilizza simulazioni basate sui modelli del sistema, disponibili durante le varie fasi dello sviluppo, per ottenere le tracce di potenza necessarie per la valutazione degli eventuali punti nella computazione sensibili agli attacchi. In particolare, sono stati considerati due specifici modelli, normalmente utilizzati dal progettista per validare il comportamento del sistema durante la fase di design: il modello disponibile dopo la fase di sintesi e quello ottenuto dopo l’implementazione. Una considerevole parte del lavoro svolto è stata dedicata all’analisi delle diversità dei risultati ottenuti dall’utilizzo dei due modelli e delle conseguenze di queste ultime sull’efficacia della valutazione delle vulnerabilità del sistema. La metodologia proposta è stata validata tramite un’implementazione architetturale completamente compatibile con la specifica OpenRisc 1000. I risultati ottenuti mostrano che entrambi i modelli utilizzati risultano efficaci allo scopo di ottenere una valutazione della resistenza del sistema agli attacchi in potenza e che, al crescere del livello di dettaglio della descrizione del design, non corrisponde automaticamente una migliore identificazione delle eventuali vulnerabilità
An FPGA design methodology to measure the information side-channel leakage
BREVI, MATTEO
2017/2018
Abstract
Modern embedded systems has started to gain an increasing popularity since the advent of Internet of Things (IoT), thanks to the fact that IoT paradigm involves a capillary distribution of smart objects, which are responsible for collecting and sharing information over the internet, as well as interacting with the surrounding environment. Such large number of interconnected objects introduces a wide range of security risks, mostly due to their peculiar nature: indeed, differently from the common digital systems, they are strongly exposed to attacks led by someone having physical access to them, given the context in which they normally operate. This class of attacks, known as Side Channel Attack (SCA), exploits the intrinsic link between the computation and one or more physical parameters of the system itself: to this end, one of the most prominent source of information is the power consumption of the devices. Typically, the evaluation of the resistance of the system against this type of attacks is performed post-manufacturing. This scenario is far from ideal: indeed, if the device is found vulnerable and a fix is required, it is almost impossible to avoid an increase of the development costs and of the time to market. Moreover, it is worth noticing that implementing countermeasures against power attacks deteriorates parameters, such as performances and the energy consumption, which in IoT devices shall usually meet compelling requirements. It is thus crucial to introduce the concept of system security starting from the early phases of the design flow, so that it can be evaluated as all the other parameters that determine the goodness of the design. This thesis presents a design methodology for Field Programmable Gate Array, FPGA, one of the most promising technology for IoT applications, that extends the common design flow with functionalities required to correctly evaluate the vulnerabilities to power attacks. The proposed methodology leverages simulations on the design models available during all the stages of the design flow to extract the power traces which are essential for the evaluation of the security sensitive points during the computation. In particular, two specific design models, commonly adopted by the designer to validate the system behavior at design time, have been employed: the model available after the synthesis phase and the one ready after the implementation stage. A relevant part of the work has been dedicated to the analysis of the impact of employing such models and of the consequences they have on the effectiveness of the vulnerability assessment. The proposed methodology has been validated against a fully compliant OpenRisc 1000 implementation. The obtained results show that both the employed models are effective for the evaluation of the resistance of the system to power attacks, and that, increasing the detail level of the design description, does not automatically produces a better detection of the vulnerabilities.| File | Dimensione | Formato | |
|---|---|---|---|
|
2018_12_brevi.pdf
accessibile in internet solo dagli utenti autorizzati
Descrizione: Thesis text
Dimensione
1.36 MB
Formato
Adobe PDF
|
1.36 MB | Adobe PDF | Visualizza/Apri |
I documenti in POLITesi sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
https://hdl.handle.net/10589/144686