Today, while networking technologies in terms of high transmission speed and performance are getting more advanced, the distribution of resources among consumers is still a big challenge for network engineers. This is the point from where the need for fairness borns. Up to now, many algorithms and methodologies e.g. Fair Queuing (FQ), Weighted Fair Queuing (WFQ), Priority Assignment (PA), and Dynamic Queue Assignment (DQA), have been used to deal with the fairness problem, by providing their rationales, but, still there are serious uncertainties with them. As a solution for these issues and reaching a very approximate fair condition for all flows, a novel method is introduced which is a superset of mentioned algorithms called Fair Dynamic Priority Assignment (FDPA). In this thesis, I implemented the first prototype of FDPA in a physical networking device. The origin of the idea comes from the capacity of the Software-defined networking(SDN) concept and the programmability of data planes. For this implementation, I took advantage of the NetFPGA-SUME board as a programmable switching device, and the programs are written in HDL(Verilog) and programming protocol-independent packet processors(P4). Finally, I did a series of tests for various scenarios, and also, I examined the feasibility of the implementation of this idea on the mentioned device, to clarify the issues related to future developments.
Mentre le tecnologie di rete stanno diventando sempre più avanzate per velocità di trasmissione e per prestazioni, la distribuzione delle risorse tra gli utenti è ancora una grande sfida per gli ingegneri della rete. È a questo punto che nasce l'esigenza della equità (fairness) della rete. Fino ad oggi molti algoritmi e metodologie, ad esempio "Fair Queuing" (FQ), "Weighted Fair Queuing" (WFQ), "Priority Assignment" (PA) e "Dynamic Queue Assignment" (DQA), sono stati usati per trattare il problema dell'equità nella rete, fornendo le proprie logiche, ma sussistono ancora gravi difetti e incertezze. Come soluzione a questi problemi e per raggiungere una condizione molto vicina all'equità per tutti i flussi, si introduce un nuovo metodo che è un sovrainsieme degli algoritmi menzionati, ed è chiamato "Fair Dynamic Priority Assignment" (FDPA). In questa tesi ho implementato il primo prototipo di FDPA in un dispositivo di rete. L'origine dell'idea è nata grazie alle proprità del concetto di "Software-Defined Networking" (SDN) ed alla programmabilità dei piani di dati (data planes). Per questa implementazione ho sfruttato la scheda "NetFPGA-SUME" come dispositivo di switching programmabile, e i programmi sono stati scritti principalmente in HDL (Verilog) e ”Programming Protocol-independent Packet Processors (P4)”. Infine ho fatto una serie di test con diversi scenari, e ho anche esaminato la fattibilità dell'attuazione di questa idea sul dispositivo menzionato, per chiarire le questioni relative ad eventuali sviluppi futuri.
Design and implementation of fair dynamic priority assignment using software-defined networking and stateful forwarding plane
BAKHTIAR, ALI
2018/2019
Abstract
Today, while networking technologies in terms of high transmission speed and performance are getting more advanced, the distribution of resources among consumers is still a big challenge for network engineers. This is the point from where the need for fairness borns. Up to now, many algorithms and methodologies e.g. Fair Queuing (FQ), Weighted Fair Queuing (WFQ), Priority Assignment (PA), and Dynamic Queue Assignment (DQA), have been used to deal with the fairness problem, by providing their rationales, but, still there are serious uncertainties with them. As a solution for these issues and reaching a very approximate fair condition for all flows, a novel method is introduced which is a superset of mentioned algorithms called Fair Dynamic Priority Assignment (FDPA). In this thesis, I implemented the first prototype of FDPA in a physical networking device. The origin of the idea comes from the capacity of the Software-defined networking(SDN) concept and the programmability of data planes. For this implementation, I took advantage of the NetFPGA-SUME board as a programmable switching device, and the programs are written in HDL(Verilog) and programming protocol-independent packet processors(P4). Finally, I did a series of tests for various scenarios, and also, I examined the feasibility of the implementation of this idea on the mentioned device, to clarify the issues related to future developments.| File | Dimensione | Formato | |
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Thesis.pdf
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Descrizione: Thesis booklet
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https://hdl.handle.net/10589/148554