Demand to the flash memories is increased in recent years due to the increased role of technology in our lives. For almost all of the technological devices used in daily life, flash memories are essential. During flash memory operation, due to the requirement for voltage values higher/lower than power supply, special circuitries which are charge pumps should be implemented. The charge pump is a DC-DC converter that generates a higher/lower voltage than the supply voltage. The aim of this project is to identify the most suitable charge pump architecture for NAND flash memories with given design requirements. Two different charge pump architectures which are state of art are benchmarked and compared. Modifications to these architectures which are suggested in the literature are also implemented and compared. In this thesis, apart from the state of art charge pump architectures and their already suggested modifications, new modification ideas are introduced in order to increase performance and suitability of the charge pump architectures to the NAND flash memories. The results of these modifications, both theoretically and as a simulation result, are reported. Finally, new charge pump architecture introduced and designed and its comparably enhanced performance in some cases is represented. In this thesis, used technology node have not mentioned and aspect ratio of transistors in the architectures have shown with only ratios (not exact values) due to the confidentiality agreement. The thesis organized as follows; in Chapter 1, introduction and literature review is presented for NAND flash memories and charge pumps. In Chapter 2, design specifications and overall architecture are shown. In Chapter 3 and 4, Pelliconi and PMOS CTS charge pump architectures which are state of art are analyzed and new modification ideas to this architectures are represented. In Chapter 5, new charge pump architecture, NMOS CTS is analyzed. In Chapter 6, all architectures are compared in terms of output resistance, power efficiency, maximum output voltage, back charge and power consumption.
La domanda di memorie flash da parte del mercato è in costante aumento negli ultimi anni grazie al ruolo crescente della tecnologia nelle nostre vite. In molti prodotti elettronici comunemente usati le memorie flash NAND svolgono un ruolo essenziale. Per il corretto funzionamento le memorie flash necessitano di valori di tensione superiori / inferiori rispetto alla tensione di alimentazione. Questi valori di tensione sono generati internamente al chip di memoria mediante circuiti elettronici noti come pompe di carica. La pompa di carica è un circuito convertitore CC-CC che genera una tensione superiore o inferiore rispetto alla tensione di alimentazione. Lo scopo di questo progetto di tesi è quello di identificare l'architettura della pompa di carica più consona per l’impiego in memorie flash NAND tenendo conto dei requisiti di progettazione richiesti. Due diverse architetture di pompe di carica note in letteratura sono state implementate, analizzate e confrontate mediante simulazioni spice. Alcune modifiche riportate in letteratura e alcune nuove proposte di modifica a queste strutture, al fine di migliorarne le prestazioni o l’adattabilità ai requisiti richiesti nelle memorie flash NAND, sono state implementate ed analizzate sia a livello teorico che mediante simulazioni. Inoltre, è stata introdotta, progettata e ottimizzata una nuova architettura di pompa di carica e confrontata con le architetture precedentemente analizzate. In questa tesi, il nodo della tecnologia usata non è riportato esplicitamente a causa dell’accordo di riservatezza in essere ma sono comunque riportate le proporzioni dei vari transistori utilizzati per lo sviluppo delle varie architetture. La tesi è organizzata come segue: il capitolo 1 riporta una presentazione della letteratura analizzata sulle pompe di carica e sulle memorie flash NAND; nel capitolo 2 sono illustrate le specifiche di progettazione e l'architettura generale di una pompa di carica; nei capitoli 3 e 4 vengono analizzate due architetture di pompa di carica note in letteratura come “Pelliconi charge pump” e “PMOS CTS charge pump” e vengono proposte nuove idee di modifica a queste strutture; nel capitolo 5 viene introdotta una nuova architettura di pompa di carica “NMOS CTS charge pump” mentre nel capitolo 6 tutte le architetture analizzate vengono confrontate fra loro in termini di resistenza di uscita, efficienza di potenza, massima tensione di uscita, back charge e consumo.
Novel charge pump architectures for NAND flash memories
AKER, ONUR
2018/2019
Abstract
Demand to the flash memories is increased in recent years due to the increased role of technology in our lives. For almost all of the technological devices used in daily life, flash memories are essential. During flash memory operation, due to the requirement for voltage values higher/lower than power supply, special circuitries which are charge pumps should be implemented. The charge pump is a DC-DC converter that generates a higher/lower voltage than the supply voltage. The aim of this project is to identify the most suitable charge pump architecture for NAND flash memories with given design requirements. Two different charge pump architectures which are state of art are benchmarked and compared. Modifications to these architectures which are suggested in the literature are also implemented and compared. In this thesis, apart from the state of art charge pump architectures and their already suggested modifications, new modification ideas are introduced in order to increase performance and suitability of the charge pump architectures to the NAND flash memories. The results of these modifications, both theoretically and as a simulation result, are reported. Finally, new charge pump architecture introduced and designed and its comparably enhanced performance in some cases is represented. In this thesis, used technology node have not mentioned and aspect ratio of transistors in the architectures have shown with only ratios (not exact values) due to the confidentiality agreement. The thesis organized as follows; in Chapter 1, introduction and literature review is presented for NAND flash memories and charge pumps. In Chapter 2, design specifications and overall architecture are shown. In Chapter 3 and 4, Pelliconi and PMOS CTS charge pump architectures which are state of art are analyzed and new modification ideas to this architectures are represented. In Chapter 5, new charge pump architecture, NMOS CTS is analyzed. In Chapter 6, all architectures are compared in terms of output resistance, power efficiency, maximum output voltage, back charge and power consumption.| File | Dimensione | Formato | |
|---|---|---|---|
|
Novel Charge Pump Architectures for NAND Flash Memories.pdf
non accessibile
Descrizione: Thesis Report
Dimensione
4.03 MB
Formato
Adobe PDF
|
4.03 MB | Adobe PDF | Visualizza/Apri |
I documenti in POLITesi sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
https://hdl.handle.net/10589/149936