Abstract The objective of most industrial processes is to increase efficiency and reduce production cost. This can be achieved by increasing the size of installation and increasing the power of all electrical machines. One of the way to achieved increase in power of all electrical machines, is the use of power multilevel inverter. The possibility to connect power converter directly or indirectly to medium-voltage network have led to the development of various multilevel power converter such as cascaded H-bridge power converter with separated dc-source, diode clamped (NPC converter) and flying capacitor (capacitor clamped converter) for high power application. In this thesis work, the analysis and design procedures of a diode clamped multilevel inverter are presented. The advantage of diode clamped multilevel inverter (NPC) over other types of multilevel converter such as the cascade H-bridge and flying capacitor, is that all phases share a common dc-bus voltage which minimizes the capacitance requirement of the inverter. This reason makes a back-to-back topology not only possible but also for uses, such as high-voltage back-to-back interconnection or an adjustable speed drive. However, one of the technical draw back of the diode clamped multilevel inverter (DCMLI) is the dc-capacitor voltage imbalances, which occurs each time the load at the output of the inverter draws a non-zero real power .i.e. cos(∅)≠0. To solve this problem of the dc-capacitor voltage imbalance in DCMLI, an auxiliary capacitor voltage balancing circuit was proposed in this thesis, for dc-capacitor voltage balancing for a 5-level and 7-level diode clamped multilevel inverter (DCMLI).The auxiliary circuit uses an inductance which accumulate temporary the excess energy from the capacitor with the higher voltage(more than its ideal voltage) and transfer this energy to the nearest adjacent capacitor with lower voltage, thereby equalizing the voltage between these capacitors. The design procedure of the required inductance that makes-up the auxiliary capacitor voltage balancing circuit was carried out and simulation was performed using Matlab/Simulink, to verify its effectiveness. The simulation result shows the effectiveness of the proposed auxiliary circuit, not just in balancing the dc-capacitor voltages, but also was effective in THD reduction of the output voltage, current waveform of both the five-level and seven-level DCMLI.
Sintesi L’obiettivo delle industrie è quello di aumentare l’efficienza nel processo di lavoro, riducendo il costo delle produzione. Questi obiettivi possono essere raggiunti aumentando sia la capacità di produzione che le potenze delle macchine di produzione. L’aumento delle potenze delle macchine di produzione può essere ottenuto tramite l’utilizzo dei convertitori di potenza. Sono stati svillupati negli anni passati diversi tipi di convertitori di potenza tra cui: cascaded H-bridge power converter, flying capacitor(capacitor clamped converter) e diode clamped converter. In questo elaborato viene presentata l’analisi e la progettazione del convertitore NPC(Diode clamped converter). Purtroppo un problema di questo convertitore è la presenza delle tensioni sbilanciate sui condensatori, quando il carico all’uscita del convertitore richiede una potenza reale diversa da zero(cos〖(∅)≠0〗. Infatti se non regulate,le tensione possono danneggiare il convertitore. Questa tesi propone un circuito ausiliario per risolvere il problema degli sbilanciamenti delle tensioni sui condensatori del convertitore NPC . Il circuito ausiliario è composto da induttanze e dagli interruttori IGBTs. L’induttanza ha il compito di accumulare l’energia in eccesso proveniente dal condensatore con tensione più altà (più di quella ideale del condensatore) trasferendola a un condensatore più vicino con tensione minore. In questa tesi sono state approfondite delle procedure di progettazione del circuito proposto. I risultati delle simulazioni hanno dimostrato che il circuito ausiliaro proposto in questa tesi è efficace sia nel bilanciare le tensioni dei condensatori che nella riduzione delle distorsioni armoniche nelle tensioni e corrente di uscita del convertitore NPC .
Design and analysis of diode clamped multilevel inverter
OBASOGIE, SCOTT OSAIGBOVO
2019/2020
Abstract
Abstract The objective of most industrial processes is to increase efficiency and reduce production cost. This can be achieved by increasing the size of installation and increasing the power of all electrical machines. One of the way to achieved increase in power of all electrical machines, is the use of power multilevel inverter. The possibility to connect power converter directly or indirectly to medium-voltage network have led to the development of various multilevel power converter such as cascaded H-bridge power converter with separated dc-source, diode clamped (NPC converter) and flying capacitor (capacitor clamped converter) for high power application. In this thesis work, the analysis and design procedures of a diode clamped multilevel inverter are presented. The advantage of diode clamped multilevel inverter (NPC) over other types of multilevel converter such as the cascade H-bridge and flying capacitor, is that all phases share a common dc-bus voltage which minimizes the capacitance requirement of the inverter. This reason makes a back-to-back topology not only possible but also for uses, such as high-voltage back-to-back interconnection or an adjustable speed drive. However, one of the technical draw back of the diode clamped multilevel inverter (DCMLI) is the dc-capacitor voltage imbalances, which occurs each time the load at the output of the inverter draws a non-zero real power .i.e. cos(∅)≠0. To solve this problem of the dc-capacitor voltage imbalance in DCMLI, an auxiliary capacitor voltage balancing circuit was proposed in this thesis, for dc-capacitor voltage balancing for a 5-level and 7-level diode clamped multilevel inverter (DCMLI).The auxiliary circuit uses an inductance which accumulate temporary the excess energy from the capacitor with the higher voltage(more than its ideal voltage) and transfer this energy to the nearest adjacent capacitor with lower voltage, thereby equalizing the voltage between these capacitors. The design procedure of the required inductance that makes-up the auxiliary capacitor voltage balancing circuit was carried out and simulation was performed using Matlab/Simulink, to verify its effectiveness. The simulation result shows the effectiveness of the proposed auxiliary circuit, not just in balancing the dc-capacitor voltages, but also was effective in THD reduction of the output voltage, current waveform of both the five-level and seven-level DCMLI.File | Dimensione | Formato | |
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SCOTT-THESIS ON NPC CONVERTER.pdf
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Descrizione: DIODE CLAMPED MULTILEVEL INVERTER
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https://hdl.handle.net/10589/165608