This thesis dissertation reflects the research activity carried out from October 2019 to July 2020 at the Semiconductor Devices and Integrated Circuits Laboratory of Politecnico di Milano in Como. The main objective of the work was to experimentally test a newly introduced gain dispersion reduction module inside a research-grade high resolution read-out ASIC (Application Specific Integrated Circuit) for X and γ ray CdZnTe/CdTe detectors, called ALTAIR, fabricated in AMS CMOS 0.35 μm technology. The gain dispersion reduction name stands for a module capable of finely tuning the gain of the analog read-out chain to compensate for unavoidable dispersions related to CMOS process variability. Gain dispersion of readout channels as large as 50% can be easily found from channel to channel on the same chip and on different chips. This can generate problems in large format systems as for example the readout electronics of radiation detectors for X-ray space telescopes constituted by tens of thousands of channels. Although a compensation of gain dispersion can be done, also off-line, on the output digital data, this does not avoid an oversizing of the ASIC output dynamic range to avoid signal saturation, together with a significant resolution loss in the analog-to-digital conversion. Large multi-channel read-out systems would benefit from the ability to equalize the gain of all channels to approximately the same value by directly acting on the analog section of the signal processor. A test chip featuring the first prototype of the GDR module was designed in a previous thesis work and was available at the beginning of this thesis for a first characterization All phases of the characterization process have been carried out: from the design and implementation of the printed circuit board for testing, to the analysis and justification of experimental data. The chip characterization was performed in standalone mode, i.e. without mounting a detector but exploiting an available input test signal. Once the assessment of the module performance was completed, a new design iteration of the module was deemed necessary due to some unsatisfactory performance in terms of dispersion and linearity, uncovered during the experimental characterization, originating from layout-dependent device mismatch that were not predicted by simulation data. The cause for these encountered critical aspects has been pinpointed after a deep analysis of experimental evidence, coupled with an extensive study in open scientific literature, serving as the backbone of the proposed hypothesis. The optimization of the module is made both at design and at layout level, utilizing Cadence Virtuoso ADE Product Suite, to improve its performance in terms of linearity and device matching. The new IC implementation process was followed until tape-out, after which the project was sent out for fabrication and future testing.
Questa Tesi è il risultato dell’attività di ricerca condotta da ottobre 2019 a luglio 2020 al laboratorio di Dispositivi a Semiconduttore e Circuiti Integrati del Politecnico di Milano a Como. Il principale obbiettivo del lavoro è stato quello di testare sperimentalmente un modulo per la riduzione della dispersione di guadagno, compreso in un ASIC da ricerca ad alta risoluzione per rivelatori CdZnTe/CdTe per raggi X e γ, denominato ALTAIR, fabbricato in tecnologia AMS 0.35 μm CMOS. La denominazione riduzione della dispersione di guadagno si riferisce ad un modulo capace di calibrare finemente il guadagno della catena di lettura analogica per ridurre la sua inevitabile dispersione statistica, dovuta alla variabilità di processo presente nelle tecnologie CMOS. Dispersioni di guadagno fino al 50% posso essere riscontrati sullo stesso chip o su chip differenti. Questo può essere fonte di problemi in sistemi di ampio formato, come ad esempio l’elettronica di lettura di rivelatori di radiazione per telescopi spaziali a raggi X costituiti da decine di migliaia di canali. Anche se una compensazione della dispersione di canale può essere fatta numericamente sul dato digitale, questo non evita un necessario sovradimensionamento del range dinamico di uscita dell’ASIC per evitare la saturazione del segnale, assieme ad una perdita di risoluzione significativa nella conversione analogico-digitale. Grandi sistemi multicanale beneficerebbero dall’abilità di equalizzare il guadagno di tutti i canali a circa lo stesso valore, agendo direttamente sulla sezione analogica del processore di segnale. Un chip di test con un primo prototipo del modulo GDR è stato progettato in un precedente lavoro di tesi ed era disponibile all’inizio dell’attività di tesi per una prima caratterizzazione. Tutte le fasi del processo di caratterizzazione sono state condotte: dalla progettazione e implementazione del circuito stampato per condurre i test, all’analisi e giustificazione dei dati sperimentali. La caratterizzazione del circuito integrato è stata condotta in modalità standalone, senza montare un rivelatore ma sfruttando l’apposito segnale di test. Una volta completata la valutazione delle prestazioni del modulo, si è ritenuto di condurre una nuova iterazione di progetto, a causa di alcune prestazioni non soddisfacenti in termini di dispersione e linearità, riscontrate durante la caratterizzazione sperimentale, originatesi da fonti di mismatch legate al layout circuitale non predette dai dati di simulazione. Dopo una profonda analisi delle evidenze sperimentali, accoppiata ad un estensivo studio della letteratura scientifica disponibile per meglio supportare la tesi proposta, la causa responsabile delle criticità riscontrate è stata individuata. L’ottimizzazione del modulo è stata condotta sia a livello progettuale che a livello di layout circuitale, utilizzando il software Cadence Virtuoso ADE Product Suite, per migliorare le sue prestazioni in termini di linearità e matching dei dispositivi. La nuova implementazione è stata portata a termine in tutte le sue fasi, dopo le quali il progetto è stato mandato in fabbricazione per future attività sperimentali.
A CMOS analog processor for gain dispersion reduction in multi-channel readout ASICs for X and Gamma ray detectors : characterization and design optimization
QUERCIA, JACOPO
2019/2020
Abstract
This thesis dissertation reflects the research activity carried out from October 2019 to July 2020 at the Semiconductor Devices and Integrated Circuits Laboratory of Politecnico di Milano in Como. The main objective of the work was to experimentally test a newly introduced gain dispersion reduction module inside a research-grade high resolution read-out ASIC (Application Specific Integrated Circuit) for X and γ ray CdZnTe/CdTe detectors, called ALTAIR, fabricated in AMS CMOS 0.35 μm technology. The gain dispersion reduction name stands for a module capable of finely tuning the gain of the analog read-out chain to compensate for unavoidable dispersions related to CMOS process variability. Gain dispersion of readout channels as large as 50% can be easily found from channel to channel on the same chip and on different chips. This can generate problems in large format systems as for example the readout electronics of radiation detectors for X-ray space telescopes constituted by tens of thousands of channels. Although a compensation of gain dispersion can be done, also off-line, on the output digital data, this does not avoid an oversizing of the ASIC output dynamic range to avoid signal saturation, together with a significant resolution loss in the analog-to-digital conversion. Large multi-channel read-out systems would benefit from the ability to equalize the gain of all channels to approximately the same value by directly acting on the analog section of the signal processor. A test chip featuring the first prototype of the GDR module was designed in a previous thesis work and was available at the beginning of this thesis for a first characterization All phases of the characterization process have been carried out: from the design and implementation of the printed circuit board for testing, to the analysis and justification of experimental data. The chip characterization was performed in standalone mode, i.e. without mounting a detector but exploiting an available input test signal. Once the assessment of the module performance was completed, a new design iteration of the module was deemed necessary due to some unsatisfactory performance in terms of dispersion and linearity, uncovered during the experimental characterization, originating from layout-dependent device mismatch that were not predicted by simulation data. The cause for these encountered critical aspects has been pinpointed after a deep analysis of experimental evidence, coupled with an extensive study in open scientific literature, serving as the backbone of the proposed hypothesis. The optimization of the module is made both at design and at layout level, utilizing Cadence Virtuoso ADE Product Suite, to improve its performance in terms of linearity and device matching. The new IC implementation process was followed until tape-out, after which the project was sent out for fabrication and future testing.| File | Dimensione | Formato | |
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https://hdl.handle.net/10589/166930