To face the explosive growth in data-rates demand pushed by modern applications such as cloud computing and video streaming services, the modern communication infrastructure is moving towards mm-Wave frequencies in the quest for larger bandwidths. Among the most prominent mm-Wave wireless applications areWiGig and E-band wireless-backhaul. The operating frequency of transceivers employed in these applications pose extremely challenging requirements on the frequency synthesizer integrated jitter. Hence, the research for architectures able to satisfy the demand for such low jitter levels is of great interest. The ultimate performances achievable by traditional synthesizer architectures are inextricably linked to the technology employed for their design. Steeper edges and higher quality factors being necessary conditions for low jitter levels. To exceed the technological limitations it is necessary to introduce some innovation at the architectural level. One such example being that of multi-core oscillators. For this reason, this thesis investigates multi-core solutions (oscillators and phase-locked loops) to exploit the noise-power tradeoff and synthesize low noise carriers. The synthesizers presented in this thesis operate in the tens of GHz range and are thought as part of an LO system comprising a frequency multiplier, to exploit the better quality factors available at lower frequencies. Initially, a 30GHz frequency synthesizer based on a new digital sub-sampling architecture is investigated. This mm-Wave phase-locked loop (PLL) reduces the gap in terms of jitter-power FoM between mm-Wave synthesizers and sub-6GHz RF ones. To this end, the PLL combines: a subsampling bang-bang phase-detector, a low-power divide-by-six prescaler with a novel injection scheme, and a digital technique reducing the output range of the digital-to-time converter. The integrated rms jitter is 197fsrms (30kHz-10MHz). Fractional spurs measured at the output of the 5GHz prescaler are below -54dBc. The power consumption is 35mW from a 1.2V power supply, leading to a FoM = -238.6dB which advanced state of the art at the time of publication. Following, an analysis of jitter performances of digital PLLs employing multi-bit timedigital-converters with mid-rise characteristic and bang-bang phase-detector is presented. Closed form expressions for jitter reduction as function of the number of thresholds is given. A 2-bits phase-detector (three thresholds) proved being the best compromise between jitter reduction and complexity increase. The thesis continues dealing with multi-core oscillators and PLLs for spot-noise and jitter reduction. The multi-core oscillators based approach showed an inherent complexity which undermines the design and integration of the overall system impairing its performances. To avoid such complexities architectures based on multi-core PLLs (both based on coupling loop filters and power combiners) are proposed. A novel coupled PLLs architecture is proposed which is able to enforce the coupling mechanism on the reference path. The proposed circuit consists of two, or more, standard loops coupled via an additional phase detector. The work shows how to derive a set of design parameters that grant the desired performances and the conditions under which phase noise reduction is obtained. The procedure is verified by simulations. Finally, a test-chip implementing a 20GHz dual-core power-scalable PLL architecture embedding two 192dB FoM DCOs is presented, which advances the state of the art in terms of oscillator’s FoM inside a multi-core system. The synthesizer features i) a powercombiner based dual-core PLL architecture ii) an offset correction loop iii) an efficient harmonic extraction scheme. The synthesizer achieves 206fsrms and 174fsrms (1kHz-10MHz) consuming 18mW and 42.6mW in the single-core and dual-core configurations respectively. The resulting FoM in the two cases are -241dB and -238.9dB. Fractional spurs, at the divided 5GHz output, are lower than -40dBc.
Per soddisfare la domanda di data-rates sempre più elevati spinta da applicazioni quali il cloud-computing e lo streaming video, la moderna infrastruttura di telecomunicazione si sta spostando verso le frequenze ad onde millimetriche alla ricerca di bande elevate. Tra le applicazioni wireless di maggiore rilevanza spiccano l’E-band Wireless Backhaul ed il WiGig. Le frequenze operative dei trasmettitori adibiti a tali applicazioni pongono dei requisiti estremamente stringenti sul sintetizzatore di frequenza (realizzato tipicamente tramite loop ad aggancio di fase, o PLL) in termini di jitter integrale. Dunque, la ricerca di architetture in grado di raggiungere bassissimi valori di jitter è di grande interesse. Le performance ultime raggiungibili dai tradizionali sintetizzatori di frequenza sono intrinsecamente legate alla tecnologia impiegata per la loro realizzazione. Fronti ripidi ed alti fattori di qualità sono fattori essenziali per raggiungere performance eccellenti. Per superare le limitazioni imposte dalla tecnologia è necessario introdurre innovazione a livello architetturale, un esempio del quale sono gli oscillatori multi-core. Per questa ragione, in questa tesi vengono investigate le soluzioni multi-core (sia oscillatori che sintetizzatori di frequenza) al fine di sfruttare il trade-off rumore-potenza per sintetizzare carrier a bassissimo jitter. I sintetizzatori presentati in questa tesi operano nel range della decina di GHz e sono pensati per esse parte di un sistema di distribuzione dell’oscillatore locale seguiti da un moltiplicatore di frequenza. Inizialmente viene presentato un sintetizzatore di frequenza a 30GHz basato su una architettura sub-sampling digitale. Questo sintetizzatore a mm-Wave, al momento della pubblicazione, ha migliorato il gap dello stato dell’arte in termini della figura di merito (FoM) rumore-potenza tra i sintetizzatori RF sub-6GHz e quelli mm-Wave. Ciò è stato possibile grazie all’impiego di: un rilevatore di fase sub-sampling binario, un innovativo divisore per sei injection locked ed una tecnica per la riduzione del range del digital-to-time converter. Il jitter integrato è di 197fsrms (30kHz-10MHz). Le spurie frazionarie misurate all’uscita a 5GHz del prescaler sono inferiori a -54dBc. Il consumo di potenza è di 35mW da una supply ad 1.2V, garantendo una FoM di -236.6dB. In seguito viene presentata una analisi del jitter dei PLL digitali facenti uso di rilevatori di fase multi-bit con caratteristica mid-rise. Lo studio fornisce espressioni in forma chiusa della riduzione del jitter integrale in funzione del numero di soglie. L’analisi condotta ha dimostrato come un rilevatore di fase a due bit (tre soglie) è il miglior compromesso tra riduzione del rumore ed incremento della complessità. La tesi continua discutendo l’implementazione di un PLL con oscillatore multi-core per migliorare lo spot noise e ridurre il jitter integrale. Questo approccio ha presentato delle complessità intrinseche che hanno minato il design compromettendone le performance. Per evitare le problematiche connesse a questo approccio viene proposta una architettura basata su PLL multi-core (sia basati su combinatore di potenza che su loop di accoppiamento). Viene proposta una nuova architettura di PLL accoppiati tramite loop ausiliario, che estende la scalabilità del rumore di fase al cammino del riferimento. L’architettura consiste di due o più loop accoppiati tra di loro tramite un rilevatore di fase ed un filtro d’anello digitale aggiuntivo. Verrà discusso come derivare un set di parametri di design che garantiscano le performance desiderate e le condizioni per le quali è garantita la riduzione del rumore. La procedura è verificata tramite simulazioni. Infine, è stato implementato un test-chip di un PLL dual-core a 20GHz con oscillatori digitali aventi una FoM di 192dB, avanzando lo stato dell’arte in termini di FoM dell’oscillatore in un sistema multi-core. Il sintetizzatore include: 1) Una architettura dual core basata su combinatore di potenza 2) Un loop di correzione dell’offset 3) Un efficiente schema di estrazione della seconda armonica dell’oscillatore. Il sintetizzatore raggiunge un jitter integrale di 206fsrms e 174fsrms (1kHz-10MHz) nelle modalità a singolo e doppio core rispettivamente, consumando 18mW e 42.6mW. La FoM risultante nei due casi è di -241dB e -238.9dB. Le spurie frazionarie, all’uscita divisa di 5GHz, sono inferiori a -40dBc.
Multi-core frequency synthesizers for MM-wave communications
Karman, Saleh
2020/2021
Abstract
To face the explosive growth in data-rates demand pushed by modern applications such as cloud computing and video streaming services, the modern communication infrastructure is moving towards mm-Wave frequencies in the quest for larger bandwidths. Among the most prominent mm-Wave wireless applications areWiGig and E-band wireless-backhaul. The operating frequency of transceivers employed in these applications pose extremely challenging requirements on the frequency synthesizer integrated jitter. Hence, the research for architectures able to satisfy the demand for such low jitter levels is of great interest. The ultimate performances achievable by traditional synthesizer architectures are inextricably linked to the technology employed for their design. Steeper edges and higher quality factors being necessary conditions for low jitter levels. To exceed the technological limitations it is necessary to introduce some innovation at the architectural level. One such example being that of multi-core oscillators. For this reason, this thesis investigates multi-core solutions (oscillators and phase-locked loops) to exploit the noise-power tradeoff and synthesize low noise carriers. The synthesizers presented in this thesis operate in the tens of GHz range and are thought as part of an LO system comprising a frequency multiplier, to exploit the better quality factors available at lower frequencies. Initially, a 30GHz frequency synthesizer based on a new digital sub-sampling architecture is investigated. This mm-Wave phase-locked loop (PLL) reduces the gap in terms of jitter-power FoM between mm-Wave synthesizers and sub-6GHz RF ones. To this end, the PLL combines: a subsampling bang-bang phase-detector, a low-power divide-by-six prescaler with a novel injection scheme, and a digital technique reducing the output range of the digital-to-time converter. The integrated rms jitter is 197fsrms (30kHz-10MHz). Fractional spurs measured at the output of the 5GHz prescaler are below -54dBc. The power consumption is 35mW from a 1.2V power supply, leading to a FoM = -238.6dB which advanced state of the art at the time of publication. Following, an analysis of jitter performances of digital PLLs employing multi-bit timedigital-converters with mid-rise characteristic and bang-bang phase-detector is presented. Closed form expressions for jitter reduction as function of the number of thresholds is given. A 2-bits phase-detector (three thresholds) proved being the best compromise between jitter reduction and complexity increase. The thesis continues dealing with multi-core oscillators and PLLs for spot-noise and jitter reduction. The multi-core oscillators based approach showed an inherent complexity which undermines the design and integration of the overall system impairing its performances. To avoid such complexities architectures based on multi-core PLLs (both based on coupling loop filters and power combiners) are proposed. A novel coupled PLLs architecture is proposed which is able to enforce the coupling mechanism on the reference path. The proposed circuit consists of two, or more, standard loops coupled via an additional phase detector. The work shows how to derive a set of design parameters that grant the desired performances and the conditions under which phase noise reduction is obtained. The procedure is verified by simulations. Finally, a test-chip implementing a 20GHz dual-core power-scalable PLL architecture embedding two 192dB FoM DCOs is presented, which advances the state of the art in terms of oscillator’s FoM inside a multi-core system. The synthesizer features i) a powercombiner based dual-core PLL architecture ii) an offset correction loop iii) an efficient harmonic extraction scheme. The synthesizer achieves 206fsrms and 174fsrms (1kHz-10MHz) consuming 18mW and 42.6mW in the single-core and dual-core configurations respectively. The resulting FoM in the two cases are -241dB and -238.9dB. Fractional spurs, at the divided 5GHz output, are lower than -40dBc.| File | Dimensione | Formato | |
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https://hdl.handle.net/10589/169709