The scalar-point multiplication ([k]P) is the building block for Elliptic Curve Cryptography (ECC). All the algorithms for ECC use the [k]P operation, moreover the use of curves on fields with elements that can be represented in Z2 has many advantages over prime fields GF (p) (with p prime) in terms of area. This work consists of a detailed research on the design and an implementation of the [k]P operation in GF (2m). The work has been developed for STMicrolectronics with the specific aim of achieving a good area/latency compromise and with side channel protections. In order to reduce area, I analyzed the best possible implementations for the operations performed to compute the [k]P operation that offer side-channel protections. Therefore, I compared different techniques for multiplication, modular reduction and all the field operations with the specific aim of minimizing area. Finally, I implemented and compared the differences in using these different algorithms in terms of area and latency in order to suggest which particular algorithm works best on different environments. I furthermore extended the study on our implementation to side-channel attacks that can be performed against it. I first analyzed the possible characteristics that might lead to information being leaked on the power consumption channel. Then I used these characteristics in order to mount different attacks. Finally, using the information gathered from these attacks, I implemented countermeasures in order to protect our circuit from side-channel attacks and compared them in terms of what is their overhead for circuital area and latency.
La moltiplicazione scalare ([k]P) è l’elemento costitutivo della crittografia a curve ellittiche (ECC). Tutti gli algoritmi per ECC utilizzano l’operazione [k]P, inoltre l’utilizzo di curve sui campi i cui elementi possono essere rappresentati come polinomi a coefficienti in Z2, presenta molti vantaggi rispetto ai campi primi GF (p) (con p primo) in termini di area. Questo lavoro consiste in una ricerca dettagliata sul progetto e un’implementazione dell’operazione [k]P in GF (2m). Il lavoro è stato sviluppato per STMicrolectronics con l’obiettivo di avere un buon compromesso area/latenza e protezione da attacchi side-channel. Al fine di ridurre l’area, ho analizzato le migliori implementazioni possibili per le operazioni eseguite per calcolare l’operazione [k]P con resistenza ad attacchi side-channel. Pertanto, ho confrontato diverse tecniche di moltiplicazione, riduzione modulare e tutte le operazioni sulle curve ellittiche con il fine di minimizzare l’area. Infine, ho implementato un confronto delle differenze nell’utilizzo di questi diversi algoritmi in termini di area e latenza per suggerire quale particolare algoritmo funziona meglio su ambienti diversi. Ho inoltre esteso lo studio della nostra implementazione ad attacchi di tipo side-channel contro di essa. Ho quindi prima analizzato i possibili caratteristiche che potrebbero portare alla trasmissione involontaria d’informazioni tramite il canale indesiderato del consumo di energia del dispositivo. Quindi ho utilizzato questi caratteristiche per montare diversi attacchi. Infine, utilizzando le informazioni raccolte da questi attacchi, ho implementato contromisure per proteggere il nostro circuito dagli attacchi di tipo side-channel e le ho confrontate in termini di costi extra per area circuitale e latenza.
Design and implementation of a cryptographic ASIC circuit for elliptic curve scalar-point multiplications over binary fields
FERRI, FEDERICO
2020/2021
Abstract
The scalar-point multiplication ([k]P) is the building block for Elliptic Curve Cryptography (ECC). All the algorithms for ECC use the [k]P operation, moreover the use of curves on fields with elements that can be represented in Z2 has many advantages over prime fields GF (p) (with p prime) in terms of area. This work consists of a detailed research on the design and an implementation of the [k]P operation in GF (2m). The work has been developed for STMicrolectronics with the specific aim of achieving a good area/latency compromise and with side channel protections. In order to reduce area, I analyzed the best possible implementations for the operations performed to compute the [k]P operation that offer side-channel protections. Therefore, I compared different techniques for multiplication, modular reduction and all the field operations with the specific aim of minimizing area. Finally, I implemented and compared the differences in using these different algorithms in terms of area and latency in order to suggest which particular algorithm works best on different environments. I furthermore extended the study on our implementation to side-channel attacks that can be performed against it. I first analyzed the possible characteristics that might lead to information being leaked on the power consumption channel. Then I used these characteristics in order to mount different attacks. Finally, using the information gathered from these attacks, I implemented countermeasures in order to protect our circuit from side-channel attacks and compared them in terms of what is their overhead for circuital area and latency.| File | Dimensione | Formato | |
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final_delivery.pdf
Open Access dal 30/11/2024
Descrizione: Tesi + Executive Summary
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2.74 MB
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https://hdl.handle.net/10589/183460