The human brain information processing has always fascinated neuroscientists, as well as neural engineers, thanks to its ability to handle and process large amounts of data with extraordinary efficiency in terms of time and power dissipation. Thanks to these peculiarities, since the work of John Von Neumann, this organ has inspired advanced computing architectures and led to the growth of neuromorphic engineering. Several attempts to reproduce some of the biological principles acting in the human brain have been collected as neuromorphic circuits. On the other hand, quantum computers have been investigated thanks to their enhanced information-processing capability. This peculiarity makes them the best candidates to solve complex problems, otherwise intractable with classical computers. However, to work correctly and maintain the qubit state, quantum computers based on microelectronic technology require stringent operating conditions, like a cryogenic environment. In fact, at extremely low temperature the material non-idealities (like molecules thermal oscillations, collisions...) are reduced and barely affect the system performances. A cryo-neuromorphic circuit in standard CMOS technology can be envisioned as an interface and control platform for quantum computers, able to progres sively learn how to compensate the residual non-idealities and the effect of the environmental noise on the qubit state. In this Thesis work (Chapter 1 and Chapter 2) a CMOS-based spiking neural network, composed of two analog neurons and a floating-gate synaptic circuit connecting them, is considered as reference. In particular, the network exploits a learning principle called Spike Time Dependent Plasticity (STDP), in which the synaptic weight adaptation depends on the time interval between the spikes of the pre-neuron and those of the post-neuron. The network is successively expanded into a circuit comprising three neurons and two synapses. Read out buffers have been designed to measure the spiking signals and, finally, the overall circuit layout has been developed for the chip realization. The second part of the Thesis (Chapter 3 and Chapter 4) is focused on the adaptation of the network at cryogenic temperature (4.2K). The state of the art in cryogenic neural networks mainly offers superconducting nanowires as cryo-neurons, strips on thin film made in Niobium Nitride (NbN), and inductive synapses. However, a fully-silicon CMOS based neural network is preferable in terms of scalability and technological process adaptability. Hence, CMOS transistors characteristic curves at 4.2K are analyzed and ac curate models are derived. The neuron circuit has been redesigned at 4.2K and a different storage approach for the synapse, from floating gate-based to capacitance-based, has been adopted. Finally, the STDP principle occurring in this cryo-neural network is illustrated and verified through simulations.
L’abilità di processare informazioni tipica del cervello umano ha da sempre affascinato i neuroscienziati, così come gli ingegneri di reti nurali, per la sua capacità di trattare e gestire grandi quantità di dati in modo estremamente efficiente in termini di tempo e potenza dissipata. Grazie a queste caratteristiche, questo organo ha ispirato avanzate architetture di calcolo e ha portato all’ evoluzione dell’ingegneria neuromorfica. Le varie reti artificiali che tentano di riprodurre i principi del sistema nervoso umano vengono raccolte sotto il nome di circuiti neuromorfici. Dall’altro lato, la ricerca sui computer quantistici si è notevolmente approfondita grazie alla potenziata capacità di processare informazioni. Questa caratteristica rende questi dispositivi i candidati più promettenti per risolvere problemi troppo complessi per i classici computer. Purtroppo, per operare correttamente e mantenere intatto lo stato del qubit, i quantum computers basati su tecnologie microelettroniche necessitano di stringenti condizioni di lavoro, come un ambiente a temperatura criogenica. Infatti, a temperature estremamente basse le non idealità del materiale (ad esempio, le oscillazioni e le collisioni molecolari) sono ridotte e affliggono in modo trascurabile le performance del sistema. Un circuito crio-neuromorfico in tecnologia standard CMOS potrebbe essere impiegato come piattaforma di interfaccia e controllo per computer quantistici, capace di imparare progressivamente come compensare le residue non idealità e l’effetto del rumore dell’ambiente circostante sullo stato del qubit. In questa Tesi (Capitolo 1 e Capitolo 2) si considera come riferimento una rete neurale ti tipo spiking in tecnologia CMOS, composta da due neuroni analogici connessi da un circuito sinaptico di tipo floating gate. In particolare, la rete sfrutta un sistema di apprendimento di tipo Spike Time Dependent Plasticity (STDP), in cui il cambiamento del peso sinaptico è dettato dalla distanza temporale che intercorre tra i segnali di spike del neurone pre e quelli del neurone post. La rete viene ulteriormente estesa in una catena che comprende tre neuroni e due sinapsi. Successivamente, sono stati realizzati dei buffer di lettura per rilevare i segnali spiking e, infine, si è passati alla fase di layout del circuito complessivo. Nella seconda parte della Tesi (Capitolo 3 e Capitolo 4) la rete è stata adattata per operare a temperature criogeniche (4.2K). Lo stato dell’arte delle reti criogeniche neurali offre principalmente nanowires superconduttivi come crioneuroni (composte da strutture filiformi su film sottili in Nitrato di Niobio) e sinapsi induttive. Al contrario, delle reti neurali basate esclusivamente su tec nologia CMOS in silicio risultano più scalabili e adattabili ai classici processi produttivi di circuiti elettronici. Pertanto, vengono studiate le curve caratter istiche dei transistori CMOS a 4.2K e vengono ricavati modelli accurati per il design e le simulazioni. A questo punto, il circuito del neurone viene modificato per operare a 4.2K e diventa necessario un nuovo approccio di memoria sinaptica, non più floating gate, bensì capacitivo. Infine, si dimostra tramite simulazioni che il principio Spike Time Depenent Plasticity che regola l’aggiornamento sinaptico a temperatura ambiente si verifichi anche nella rete complessiva adattata a 4.2K.
Design of cryogenic CMOS-based spiking neural networks
POLIDORI, CRISTINA
2020/2021
Abstract
The human brain information processing has always fascinated neuroscientists, as well as neural engineers, thanks to its ability to handle and process large amounts of data with extraordinary efficiency in terms of time and power dissipation. Thanks to these peculiarities, since the work of John Von Neumann, this organ has inspired advanced computing architectures and led to the growth of neuromorphic engineering. Several attempts to reproduce some of the biological principles acting in the human brain have been collected as neuromorphic circuits. On the other hand, quantum computers have been investigated thanks to their enhanced information-processing capability. This peculiarity makes them the best candidates to solve complex problems, otherwise intractable with classical computers. However, to work correctly and maintain the qubit state, quantum computers based on microelectronic technology require stringent operating conditions, like a cryogenic environment. In fact, at extremely low temperature the material non-idealities (like molecules thermal oscillations, collisions...) are reduced and barely affect the system performances. A cryo-neuromorphic circuit in standard CMOS technology can be envisioned as an interface and control platform for quantum computers, able to progres sively learn how to compensate the residual non-idealities and the effect of the environmental noise on the qubit state. In this Thesis work (Chapter 1 and Chapter 2) a CMOS-based spiking neural network, composed of two analog neurons and a floating-gate synaptic circuit connecting them, is considered as reference. In particular, the network exploits a learning principle called Spike Time Dependent Plasticity (STDP), in which the synaptic weight adaptation depends on the time interval between the spikes of the pre-neuron and those of the post-neuron. The network is successively expanded into a circuit comprising three neurons and two synapses. Read out buffers have been designed to measure the spiking signals and, finally, the overall circuit layout has been developed for the chip realization. The second part of the Thesis (Chapter 3 and Chapter 4) is focused on the adaptation of the network at cryogenic temperature (4.2K). The state of the art in cryogenic neural networks mainly offers superconducting nanowires as cryo-neurons, strips on thin film made in Niobium Nitride (NbN), and inductive synapses. However, a fully-silicon CMOS based neural network is preferable in terms of scalability and technological process adaptability. Hence, CMOS transistors characteristic curves at 4.2K are analyzed and ac curate models are derived. The neuron circuit has been redesigned at 4.2K and a different storage approach for the synapse, from floating gate-based to capacitance-based, has been adopted. Finally, the STDP principle occurring in this cryo-neural network is illustrated and verified through simulations.| File | Dimensione | Formato | |
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Descrizione: Thesis and summary, Cristina Polidori
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https://hdl.handle.net/10589/183643