Sviluppo di un flusso di verifica di segnali misti per la copertura funzionale di macrocelle FLASH

The objective of this thesis work is to present the results achieved to devise an efficient analog centric metric-driven verification (MDV) flow, enabling to consistently monitor and measure a number of analog and mixed-signal key functionalities. Leveraging the latest developments made available by Cadence with both the AMS Incisive Use Model and the analog Virtuoso platform, it was possible to tailor an advanced verification flow by utilizing proven testbench automation techniques, borrowed from the digital realm, and enhancing them with easy-to-use analog probing and monitoring functions. The outlined methodology was principally designed to fulfill a number of stringent verification requirements, overcome existing language limitations, facilitate the adoption of innovative modeling techniques and, ultimately, ensure the robustness of a non-volatile FLASH memory macrocell developed in 90nm CMOS technology. Using a host of novel methods recently introduced, it was possible to measure parameters directly sampled from SPICE, electrical and VHDL behavioral models and also benefit from top-notch observability scores in terms of current, voltage and delay values. To meet these requirements, a library of specialized checkers and monitors had to be designed to continuously ensure that analog measurements stay within specifications during mixed-signal simulations. In this case, Verilog-AMS modules modeling checking capabilities were generated with the unique features made available by SMG, the novel Schematic Model Generator now found in the Virtuoso product. The integration of SMG in the verification process simplified the design, placement, calibration and netlisting of checkers and monitors, by assembling qualified building blocks using the well-known schematic entry mode. Upfront in the flow, the unparalleled capabilities of Specman were also exploited to generate random-constrained stimuli to stress corner-case and hard-to-think scenarios. It was shown that the built Specman environment features, such as random-constrained values generation and coverage metric, fit well also in case of real values to especially express currents, potentials and delay figures in the continuous realm. Pillars of the ecosystem comprised also Incisive tools such as ePlanner and vManager, to establish a Spec-To-Closure flow that allowed to minimize the debugging effort. The Cadence irun front-end script was used to process the various language specific requirements and manage the complex simulation environment, which included SPICE netlists, Spectre command scripts, VHDL and VHDL-AMS models, ’e’ testbench and a few PSL analog assertions. In particular, the ‘e’ verification environment made use of the features delivered within the Specman-AMS integration layer. This was used to allow the analog views to be directly accessible from the ‘e’ ports, in order to stimulate and drive nodes with random generated values. Applying the MDV methodology to ensure functional coverage closure finally represented a new way to successfully confront the AMS verification demands. The adopted advanced automated testing concepts eventually led to find out uncovered design bugs and designed a modular and reusable verification flow. This thesis represents the conclusion of my one-year internship with STMicroelectronics of Agrate Brianza (Milan), in the TR&D-CCDS group, and the intent of an article presented at CDNLive EMEA Munich 2014.