A DVFS-capable heterogeneous network-on-chip architecture for power constrained multi-cores

In the multi-core era, the Networks-on-Chip (NoCs) emerged as the de-facto interconnect due to their scalability and exibility. Moreover, they strongly in uence the power consumption and performance of the entire platform, thus representing a key component to be optimized. In this scenario, sev- eral proposals in the literature presented Dynamic Voltage and Frequency (DVFS) capable NoCs to trade the power and performance metrics. However, the NoC tra c is highly variable due to the di erent phases an application crosses during its own execution. Last, the coherence protocol greatly con- tributes to the tra c shape. In a nutshell, the NoC tra c shape is mainly due to the coherence protocol, while the speci c application only in uences the tra c volume. Few seminal works discussed coherence-aware DVFS schemes for NoCs. This thesis presented a novel DVFS-capable heterogeneous NoCs. A ne grain analysis of the tra c composition enabled a further optimization of the DVFS actuation. The proposed NoC is capable to optimally balance the power and performance at low, medium and high tra c. Thus deliv- ering an holistic solution that is roughly application independent. This is achieved thanks to a load balancer module that can route the tra c to the di erent implemented physical networks. The mechanism observes the tra c load and adjusts the frequency of each physical NoC to optimally match the objective function. The novel NoC has been integrated in the Gem5 full- system simulator and compared with the baseline NoC and a state of the art DVFS-capable methodology. Results are extracted considering a 64-core architecture executing the Splash2 benchmarks. Results show that the pro- posed NoC almost provides the same performance of the performance-aware baseline NoC with an energy reduction of 30% and one third less resources.