The phase locked loop (PLL) is a fundamental element of any radio transceiver, where it is used as frequency synthesizer. In recent years, large interest of research has been devoted to the implementation of digitally-controlled PLLs, where the loop filter is implemented as core-cell based digital circuit. Moreover, the raising demand for higher operation frequency of the PLL, while maintaining the low-phase-noise performance, is also leading to an increase of the reference frequencies, which causes larger dynamic power dissipation in the digital section. In battery-powered devices, techniques to limit power dissipation while fulfilling timing constraints have to be employed. The goal of this work is to define techniques and processes that can be followed in order to reduce the power consumption of the digital part of a 65-nm CMOS digital PLL operating at 5GHz, with reference frequency of 100 MHz. The low-power optimization methods provided by the design tools and the clock gating technique are applied, reducing power consumption by 13%. In addition, other techniques as dynamic frequency scaling (DFS) and pipelining of critical paths are described and proposed. Applying the four techniques, an estimated power saving of more than 33% has been calculated.
Il phase locked loop (PLL) è un elemento fondamentale dei radio trasmettitori, dove viene usato come sintetizzatore di frequenza. Negli ultimi anni, la ricerca in questo settore è stata dedicata all’implementazione di PLLs controllati digitalmente, dove il filtro d’anello è implementato come circuito digitale basato su core-cells. In più, l’aumento delle frequenze di operazione del PLL, pur mantenendo la prestazione di basso rumore di fase, richiede un aumento anche della frequenza di riferimento che causa una maggiore dissipazione dinamica nella sezione digitale. In dispositivi alimentati a batteria, è necessario adottare tecniche che limitino tale dissipazione pur rispettando i vincoli di temporizzazione. Lobiettivo di questo lavoro è definire alcune tecniche e procedimenti che possono essere eseguiti per ridurre il consumo della parte digitale di un PLL digitale, realizzato in tecnologia CMOS di 65-nm, che opera a 5 GHz e con una frequenza di riferimento di 100 MHz. Gli algoritmi di ottimizzazione del consumo di potenza disponibili nei software commerciali di sintesi e la tecnica del clock gating sono utilizzati, riducendo il consumo del 13%. In aggiunta, altre tecniche come il dynamic frequency scaling (DFS) e il pipeline dei percorsi più critichi sono descritte e proposte. Applicando le quattro tecniche studiate, si è ottenuto un risparmio stimato superiore al 33%.
Techniques to reduce the power consumption of a CMOS digital PLL for wireless systems
MARTÍ PASCUAL, DAVID
2017/2018
Abstract
The phase locked loop (PLL) is a fundamental element of any radio transceiver, where it is used as frequency synthesizer. In recent years, large interest of research has been devoted to the implementation of digitally-controlled PLLs, where the loop filter is implemented as core-cell based digital circuit. Moreover, the raising demand for higher operation frequency of the PLL, while maintaining the low-phase-noise performance, is also leading to an increase of the reference frequencies, which causes larger dynamic power dissipation in the digital section. In battery-powered devices, techniques to limit power dissipation while fulfilling timing constraints have to be employed. The goal of this work is to define techniques and processes that can be followed in order to reduce the power consumption of the digital part of a 65-nm CMOS digital PLL operating at 5GHz, with reference frequency of 100 MHz. The low-power optimization methods provided by the design tools and the clock gating technique are applied, reducing power consumption by 13%. In addition, other techniques as dynamic frequency scaling (DFS) and pipelining of critical paths are described and proposed. Applying the four techniques, an estimated power saving of more than 33% has been calculated.File | Dimensione | Formato | |
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https://hdl.handle.net/10589/140020