The vast number of FMCW radar applications generates the demand for highly-linear, low-noise and reconfigurable fast chirp synthesizers implemented in high-volume deep sub-micron CMOS technologies. Conventional analog PLL-based chirp synthesizers realized in bipolar or BiCMOS technologies demonstrate an excellent phase noise performance, however, the modulation speed is typically limited by a narrow-bandwidth PLL. The emerging digital PLL-based synthesizers demonstrate prominent phase-noise and modulation-speed performance along with high degree of reconfigurability. The first part of the thesis derives the specification of the FMCW frequency synthesizer employing a new radar system model which was developed within the scope of this work. The proposed system model allows to analyze the impact of the chirp synthesizer impairments, such as phase noise and nonlinearity, on the performance of the FMCW radar system. The second part is focused on the analysis and design of two digital PLL prototypes in CMOS, which includes a novel pre-distortion scheme for DCO and DTC nonlinearity correction. The first implemented digital PLL-based FMCW modulator prototype is fabricated in 65-nm CMOS technology and demonstrates above-state-of-the-art performance of fast chirp synthesis. It is capable of maximum chirp slope of 173 MHz/μs and idle time of less than 200ns after an abrupt frequency step with no over or undershoot. The 23-GHz digital bang-bang PLL consuming 19.7 mA exhibits the phase noise of -100 dBc/Hz at 1MHz offset from the carrier and the worst case in-band fractional spur level is below -58 dBc. The second PLL prototype was developed and fabricated in 28 nm CMOS technology focusing on low-fractional spur operation. The novel digital pre-distortion scheme was applied to mitigate DTC nonlinearity in an 18-GHz digital bang-bang PLL which achieves in-band fractional spur level below -63dBc and exhibits the phase noise of -100 dBc/Hz at 1 MHz offset from the carrier.

The vast number of FMCW radar applications generates the demand for highly-linear, low-noise and reconfigurable fast chirp synthesizers implemented in high-volume deep sub-micron CMOS technologies. Conventional analog PLL-based chirp synthesizers realized in bipolar or BiCMOS technologies demonstrate an excellent phase noise performance, however, the modulation speed is typically limited by a narrow-bandwidth PLL. The emerging digital PLL-based synthesizers demonstrate prominent phase-noise and modulation-speed performance along with high degree of reconfigurability. The first part of the thesis derives the specification of the FMCW frequency synthesizer employing a new radar system model which was developed within the scope of this work. The proposed system model allows to analyze the impact of the chirp synthesizer impairments, such as phase noise and nonlinearity, on the performance of the FMCW radar system. The second part is focused on the analysis and design of two digital PLL prototypes in CMOS, which includes a novel pre-distortion scheme for DCO and DTC nonlinearity correction. The first implemented digital PLL-based FMCW modulator prototype is fabricated in 65-nm CMOS technology and demonstrates above-state-of-the-art performance of fast chirp synthesis. It is capable of maximum chirp slope of 173 MHz/μs and idle time of less than 200ns after an abrupt frequency step with no over or undershoot. The 23-GHz digital bang-bang PLL consuming 19.7 mA exhibits the phase noise of -100 dBc/Hz at 1MHz offset from the carrier and the worst case in-band fractional spur level is below -58 dBc. The second PLL prototype was developed and fabricated in 28 nm CMOS technology focusing on low-fractional spur operation. The novel digital pre-distortion scheme was applied to mitigate DTC nonlinearity in an 18-GHz digital bang-bang PLL which achieves in-band fractional spur level below -63dBc and exhibits the phase noise of -100 dBc/Hz at 1 MHz offset from the carrier.

Digitally-intensive frequency modulators for mm-Wave FMCW radars

CHERNIAK, DMYTRO

Abstract

The vast number of FMCW radar applications generates the demand for highly-linear, low-noise and reconfigurable fast chirp synthesizers implemented in high-volume deep sub-micron CMOS technologies. Conventional analog PLL-based chirp synthesizers realized in bipolar or BiCMOS technologies demonstrate an excellent phase noise performance, however, the modulation speed is typically limited by a narrow-bandwidth PLL. The emerging digital PLL-based synthesizers demonstrate prominent phase-noise and modulation-speed performance along with high degree of reconfigurability. The first part of the thesis derives the specification of the FMCW frequency synthesizer employing a new radar system model which was developed within the scope of this work. The proposed system model allows to analyze the impact of the chirp synthesizer impairments, such as phase noise and nonlinearity, on the performance of the FMCW radar system. The second part is focused on the analysis and design of two digital PLL prototypes in CMOS, which includes a novel pre-distortion scheme for DCO and DTC nonlinearity correction. The first implemented digital PLL-based FMCW modulator prototype is fabricated in 65-nm CMOS technology and demonstrates above-state-of-the-art performance of fast chirp synthesis. It is capable of maximum chirp slope of 173 MHz/μs and idle time of less than 200ns after an abrupt frequency step with no over or undershoot. The 23-GHz digital bang-bang PLL consuming 19.7 mA exhibits the phase noise of -100 dBc/Hz at 1MHz offset from the carrier and the worst case in-band fractional spur level is below -58 dBc. The second PLL prototype was developed and fabricated in 28 nm CMOS technology focusing on low-fractional spur operation. The novel digital pre-distortion scheme was applied to mitigate DTC nonlinearity in an 18-GHz digital bang-bang PLL which achieves in-band fractional spur level below -63dBc and exhibits the phase noise of -100 dBc/Hz at 1 MHz offset from the carrier.
PERNICI, BARBARA
GERACI, ANGELO
25-feb-2019
The vast number of FMCW radar applications generates the demand for highly-linear, low-noise and reconfigurable fast chirp synthesizers implemented in high-volume deep sub-micron CMOS technologies. Conventional analog PLL-based chirp synthesizers realized in bipolar or BiCMOS technologies demonstrate an excellent phase noise performance, however, the modulation speed is typically limited by a narrow-bandwidth PLL. The emerging digital PLL-based synthesizers demonstrate prominent phase-noise and modulation-speed performance along with high degree of reconfigurability. The first part of the thesis derives the specification of the FMCW frequency synthesizer employing a new radar system model which was developed within the scope of this work. The proposed system model allows to analyze the impact of the chirp synthesizer impairments, such as phase noise and nonlinearity, on the performance of the FMCW radar system. The second part is focused on the analysis and design of two digital PLL prototypes in CMOS, which includes a novel pre-distortion scheme for DCO and DTC nonlinearity correction. The first implemented digital PLL-based FMCW modulator prototype is fabricated in 65-nm CMOS technology and demonstrates above-state-of-the-art performance of fast chirp synthesis. It is capable of maximum chirp slope of 173 MHz/μs and idle time of less than 200ns after an abrupt frequency step with no over or undershoot. The 23-GHz digital bang-bang PLL consuming 19.7 mA exhibits the phase noise of -100 dBc/Hz at 1MHz offset from the carrier and the worst case in-band fractional spur level is below -58 dBc. The second PLL prototype was developed and fabricated in 28 nm CMOS technology focusing on low-fractional spur operation. The novel digital pre-distortion scheme was applied to mitigate DTC nonlinearity in an 18-GHz digital bang-bang PLL which achieves in-band fractional spur level below -63dBc and exhibits the phase noise of -100 dBc/Hz at 1 MHz offset from the carrier.
Tesi di dottorato
File allegati
File Dimensione Formato  
2019_02_25_PhD_Cherniak.pdf

non accessibile

Descrizione: `thesis
Dimensione 9.84 MB
Formato Adobe PDF
9.84 MB Adobe PDF   Visualizza/Apri

I documenti in POLITesi sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10589/145448