Techniques for low-jitter and low-area occupation fractional-N Frequency synthesis

In the last decades, wireless connected mobile devices became pervasive in the consumer market, thanks to the constantly increasing datarate capability and power efficiency offered by modern transceivers. To sustain the forecasted demand for higher communication bandwidth, the current research trend is to adopt complex modulation schemes at higher carrier frequencies. Moreover, to enable the expected ubiquitous diffusion of devices capable of wireless connection, the transceiver cost has to be kept low. This poses significant challenges on the frequency synthesizer implementing the transceiver local oscillator (LO), which has to operate under stringent low output jitter requirements, with low area occupation and integrated in the same CMOS technology as the digital baseband processor. In this thesis, two viable alternatives to meet these stringent requirements are presented. First, an extremely low-jitter and low area occupation frequency synthesizer is presented (Chapters 1-3), based on a sampling type-I analog PLL, which avoids the large integrating loop-filter capacitance of type-II analog PLLs. To suppress the phase detector (PD) noise contribution, a high-gain sampling PD is used, which is also functional to achieve a low reference spur, thus overcoming one of the conventional issues of type-I architectures. Recently published sampling type-I PLLs are bounded to integer-N operation, due to the phase detector narrow-range. In this work, fractional-N operation is enabled by canceling the quantization noise before phase comparison, thus overcoming this limitation and extending the benefits of sampling type-I PLLs also to fractional-N frequency synthesis. A number of digital calibration algorithms is presented to assist PLL operation and improve system performances, via the correction of analog impairments. The proposed sampling type-I PLL has been fabricated in a 28nm bulk CMOS technology process. The measured fractional-N RMS integrated jitter is 58.2 fs around a 12.5 GHz carrier, with a reference spur as low as −73.5 dBc and fractional spurs lower than −63.2 dBc. With a power consumption of 18 mW, the achieved figure-of-merit (FoM) is −252 dB, outperforming other recently published fractional-N frequency synthesizer. Thanks to the type-I architecture and the proposed digital algorithms, the area occupation is only 0.16 mm2, including decoupling capacitances and routing space, which is the smallest among published sub-100fs jitter PLLs. Second, an attractive alternative for the frequency synthesizer implementation is presented (Chapters 4-5), which relies on a fractional-N digital PLL. In the presented architecture, the phase detector is replaced with a 1-bit time-to-digital converter (TDC), and the analog loop-filter is substituted with its digital implementation, thus reducing area occupation and power consumption. Extensive use of digital adaptive algorithm is leveraged, and a technique to accurately control the PLL bandwidth, desensitizing the loop gain from any analog dependence, is proposed and analyzed. The digital bang-bang PLL has been fabricated in a 65nm CMOS process, with the emphasis on the adaptive bandwidth control performance. Even in the presence of an input noise level higher than 14 dB with respect to the nominal condition, the discussed algorithm is able to track and compensate the loop-gain variations, guaranteeing a constant PLL bandwidth with an accuracy better than 4%. The fractional-N frequency synthesizer occupies a core area of 0.22 mm2, with a 400fs RMS jitter around a 3.6GHz carrier.

In questa tesi sono presentati due progetti alternativi di sintetizzatori di frequenza frazionari in tecnologia CMOS, che soddisfano gli stringenti requisiti di rumore di fase integrato e di bassa occupazione di area imposti dai moderni standard di comunicazione wireless. La prima implementazione è basata su un anello ad aggancio di fase (PLL) analogico di tipo 1, in cui l’occupazione di area è ridotta rimuovendo un integratore nell’anello. Si è fatto uso di un rivelatore di fase a campionamento per ottenere al tempo stesso un basso jitter di uscita ed un basso livello di spuria al riferimento. La sintesi frazionaria a basso rumore è abilitata dall’utilizzo di un algoritmo di cancellazione adattativa del rumore di quantizzazione a monte del rivelatore di fase. Il PLL è stato fabbricato in tecnologia 28nm. Il jitter RMS integrato del sintetizzatore frazionario è pari a 58.2fs intorno ad una portante di 12.5GHz, con una spuria al riferimento pari a -73.5dBc e spurie frazionarie più basse di -63.2dBc. Con un consumo di potenza pari a 18mW, la figura di merito è pari a -252dB. L’occupazione di area del PLL è di soli 0.16mm2, includendo anche le capacità di decoupling e lo spazio dedicato al routing dei fili di controllo. La seconda alternativa implementa il sintetizzatore di frequenza con un PLL digitale frazionario basato su un rivelatore di fase a singolo bit. Si è fatto largo uso di algoritmi di calibrazione adattativi digitali, tra cui un algoritmo di controllo automatico della banda del PLL che è in grado di mantenere la banda costante anche in presenza di una variazione di 14dB sul livello di rumore nominale con un’accuratezza migliore del 4%. Il PLL digitale è stato implementato in tecnologia CMOS 65nm ed occupa un’area di 0.22mm2 con un jitter di 400fs RMS intorno ad una portante di 3.6GHz.