High-efficiency inductorless frequency synthesis

The roaring demand for wireless connectivity at a low price point has, in recent years, spurred the interest for highly-integrated transceiver solutions able to cut down on expensive silicon area requirements. In this context, one of the major limiting factors is generally represented by the frequency synthesizer used to generate the local oscillator signal for the transceiver. Conventionally implemented as phase-locked loops (PLLs) based around LC-oscillators, they require large amounts of area due to their use of integrated inductors, that additionally do not benefit from process scaling. However, they are generally preferred to ring-oscillator-based solutions, as they offer a superior jitter-vs-power tradeoff, which benefits the overall transceiver efficiency. A promising alternative to LC-based PLLs, which overcomes the efficiency limitations of conventional inductorless implementations, is represented by the recently proposed multiplying delay-locked loop (MDLL) architecture. Leveraging injection-locking, these kinds of systems provide aggressive filtering for ring-oscillator phase noise, ensuring both low-jitter and low-power operation in integer-N mode. Unfortunately, when extended to fractional-N frequency synthesis, MDLLs suffer from a large jitter penalty due to the noise introduced by the digital-to-time converter (DTC), which is required to perform edge-synchronization. This, in turn, leads to a substantial performance gap between integer- and fractional-N mode, which prevents their use in demanding applications. This work aims at closing the performance gap, by proposing a number of design methods and techniques to improve the jitter-power tradeoff of fractional-N MDLLs. First, an accurate time-variant model for MDLL phase noise is developed and analyzed to derive close-form expressions for the output spectrum. Then, leveraging the results obtained from this model, the MDLL jitter-power tradeoff is examined and conditions for optimum performance are identified. Finally, the DTC design tradeoffs are evaluated and a technique to significantly reduce its jitter contribution is proposed. To validate these results, a fractional-N MDLL has been designed in 65nm CMOS. The prototype occupies a core area of 0.0275 mm2 and draws 2.5 mW power from a 1.2 V supply. The maximum RMS jitter is 334 and 397 fs for the integer-N and the fractional-N case, respectively. Achieving a jitter-power figure-of-merit (FoM) of −244 dB in fractional-N mode, the proposed system effectively bridges the gap to integer-N implementations.

Questa tesi presenta metodi e tecniche per l’ottimizzazione del compromesso jitter-potenza nei sintetizzatori di frequenza frazionaria basati su oscillatore ad anello iniettato. Tali sistemi, che prendono il nome di “Multiplying Delay-Locked Loop” (MDLL), consentono di ottenere al contempo una bassa occupazione di area e un basso consumo energetico. Inizialmente, un accurato modello tempo-variante per lo spettro del rumore di fase degli MDLL è sviluppato ed analizzato, giungendo ad espressioni in forma chiusa per lo spettro di uscita. Tali espressioni sono poi sfruttate per analizzare il prodotto jitter-potenza negli MDLL, ottenendo le condizioni necessarie per massimizzare le prestazioni di tali sistemi. Infine, il compromesso jitter-potenza dei convertitori tempo-digitale è analizzato, ed una tecnica per ridurne il jitter è proposta. I risultati dell’analisi teorica sono validati attraverso il progetto di un MDLL frazionario in CMOS 65nm. Il prototipo occupa un’area di 0.0275 mm2 e dissipa una potenza di 2.5mW. Il massimo jitter RMS ottenuto è 397 fs nel caso frazionario e 334 fs in quello intero. La figura di merito nel caso frazionario corrisponde a -244 dB, che consente di colmare il divario con le implementazioni intere.