Spiking Neural Networks (SNNs) have become the most promising method to solve machine learning-based problems due to their biological and hardware plausibility and reduced complexity compared to Artificial Neural Networks (ANNs). In particular, the SNNs are the best candidate for real-time processing near the sensors, i.e., edge computing, because they can be implemented on extremely power-efficient dedicated hardware. However, the hardware implementable training algorithms for SNNs are still too immature to compete with ANN performance on real-world applications. After performing a comprehensive analysis of the learning techniques, this thesis work proposes an online training for SNNs specifically designed for floating gate CMOS technology. For the case study considered in this thesis, a simple analysis of a 3-axis accelerometer, the proposed method has proved to achieve a comparable accuracy with an ANN for edge computing. However, the SNN, when implemented on dedicated hardware, should be able to achieve power dissipation orders of magnitude less than the ANN one. The simulations and the analysis have been based on a neuromorphic chip in standard CMOS technology designed and implemented during previous thesis works.
Le Reti Neurali Spiking (SNNs) sono diventate il metodo più promettente per risolvere problemi basati sul machine learning grazie alla loro plausibilità biologica e hardware e alla loro ridotta complessità rispetto alle Reti Neurali Artificiali (ANNs). In particolare, gli SNN sono i migliori candidati per l'elaborazione in tempo reale vicino ai sensori, ovvero l'edge computing, perché possono essere implementati su hardware dedicati estremamente efficienti dal punto di vista energetico. Tuttavia, gli algoritmi di addestramento hardware implementabili per gli SNN sono ancora troppo immaturi per competere con le prestazioni delle ANNs sulle applicazioni del mondo reale. Dopo aver eseguito un'analisi completa delle tecniche di apprendimento, questo lavoro di tesi propone un allenamento online per SNN specificamente progettate per la tecnologia CMOS a gate flottante. Per il caso di studio considerato in questa tesi, una semplice analisi di un accelerometro a 3 assi, il metodo proposto ha dimostrato di ottenere una precisione comparabile a una ANN per edge computing. Tuttavia, l'SNN, se implementato su hardware dedicato, dovrebbe essere in grado di raggiungere ordini di dissipazione di potenza di grandezza inferiore a quello dell'ANN. Le simulazioni e l'analisi sono state basate su un chip neuromorfico in tecnologia CMOS standard progettato e implementato durante i precedenti lavori di tesi.
Learning in Analog Spiking Neural Network with floating gate synapses in standard CMOS technology
CAMISA, GIOVANNI
2020/2021
Abstract
Spiking Neural Networks (SNNs) have become the most promising method to solve machine learning-based problems due to their biological and hardware plausibility and reduced complexity compared to Artificial Neural Networks (ANNs). In particular, the SNNs are the best candidate for real-time processing near the sensors, i.e., edge computing, because they can be implemented on extremely power-efficient dedicated hardware. However, the hardware implementable training algorithms for SNNs are still too immature to compete with ANN performance on real-world applications. After performing a comprehensive analysis of the learning techniques, this thesis work proposes an online training for SNNs specifically designed for floating gate CMOS technology. For the case study considered in this thesis, a simple analysis of a 3-axis accelerometer, the proposed method has proved to achieve a comparable accuracy with an ANN for edge computing. However, the SNN, when implemented on dedicated hardware, should be able to achieve power dissipation orders of magnitude less than the ANN one. The simulations and the analysis have been based on a neuromorphic chip in standard CMOS technology designed and implemented during previous thesis works.File | Dimensione | Formato | |
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Executive_Summary_Giovanni_Camisa.pdf
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Tesi_Giovanni_Camisa.pdf
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https://hdl.handle.net/10589/189093