Sfoglia per Relatore
Mostrati risultati da 1 a 7 di 7
A full-system co-simulation framework to design and validate cache coherence protocols
2023/2024 GUARISCO, ADRIANO
Benchmarking high bandwidth memory on FPGA targets with RISC-V multicores
2023/2024 MOTTA, ANDREA
Design and Implementation of a convolutional neural network to locate cryptographic operations in side-channel traces
2022/2023 CHIARI, GIUSEPPE
Design and verification of a RISC-V Superscalar CPU
2022/2023 VITALI, MARCO
On microarchitectural mechanisms to combat aging in on-chip memories of convolutional neural networks accelerators
2023/2024 LANDEROS MUÑOZ, NICOLAS IGNACIO
On the effectiveness of FPGA implemented True Random Number Generators
2020/2021 GALLI, DAVIDE
A virtual prototyping methodology for timing-accurate simulation of AMS circuits
2022/2023 Vallone, Teo
Mostrati risultati da 1 a 7 di 7
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