Sfoglia per Relatore
Mostrati risultati da 1 a 13 di 13
A full-system co-simulation framework to design and validate cache coherence protocols
2023/2024 GUARISCO, ADRIANO
Benchmarking high bandwidth memory on FPGA targets with RISC-V multicores
2023/2024 MOTTA, ANDREA
Design and Implementation of a convolutional neural network to locate cryptographic operations in side-channel traces
2022/2023 CHIARI, GIUSEPPE
Design and verification of a RISC-V Superscalar CPU
2022/2023 VITALI, MARCO
Enabling NIC-accelerated multi-tenant services with P4 and isolation techniques
2023/2024 Tranquillo, Francesco Maria
FPGA acceleration of FARSE-CNN event-based vision
2024/2025 CECCHETTINI, STEFANO
Hardware-accelerated replication on FPGA-based SmartNICs
2024/2025 HANNA, KAMIL
NIC accelerated replication service
2025/2026 FONTANIVE, GIORGIO MASSIMO
A novel hybrid HBM-DDR main memory architecture for HPC systems
2025/2026 Giuliani, Niccolò
On microarchitectural mechanisms to combat aging in on-chip memories of convolutional neural networks accelerators
2023/2024 LANDEROS MUÑOZ, NICOLAS IGNACIO
On the effectiveness of FPGA implemented True Random Number Generators
2020/2021 GALLI, DAVIDE
PyTorch flow targeting RISC-V to scale DNNs on multi-cores
2025/2026 Viola, Federico
A virtual prototyping methodology for timing-accurate simulation of AMS circuits
2022/2023 Vallone, Teo
Mostrati risultati da 1 a 13 di 13
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