Sfoglia per Correlatore ZONI, DAVIDE
Mostrati risultati da 1 a 14 di 14
A DVFS-capable heterogeneous network-on-chip architecture for power constrained multi-cores
2015/2016 MARCHESE, ANDREA
A methodology to augment RTL designs with online power monitoring capability
2016/2017 CREMONA, LUCA
A network interface design for networks-on-chip in heterogeneous NUMA multicores
2014/2015 BORGHESE, LUCA
A novel cache coherence protocol to adaptively power gating LLC banks in tile-based multi-cores
2015/2016 COLOMBO, LUCA
A power gating methodology to aggressively reduce leakage power in networks-on-chip buffers
2014/2015 CANIDIO, ANDREA
An FPGA design methodology to measure the information side-channel leakage
2017/2018 BREVI, MATTEO
Deep learning techniques for side-channel cipher attacks
2021/2022 ROCCAMENA, MASSIMILIANO
Dynamic frequency scaling for Artix-7 FPGAs
2019/2020 Parravicini, Daniele
Exploring future DNUCA architectures by bridging the application behaviour and the coherence protocol support
2015/2016 BELLUSCHI, MAURO
Exploring microarchitectural design aspects of RISC CPUs in the IoT era
2017/2018 SCOTTI, GIOVANNI
Exploring the end-to-end compression to optimize the power-performance tradeoff in NoC-based multicores
2015/2016 PANCOT, FABIO
Flexible hardware design of the LEDApkc encryption for FPGA
2018/2019 GALIMBERTI, ANDREA
A methodology to automatically augment the RTL description of generic digital systems
2019/2020 Piccoli, Michele
Side-channel analysis and countermeasure of an embedded system microarchitecture
2018/2019 SACCO, ALESSIO
Mostrati risultati da 1 a 14 di 14
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